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IOSystem

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Productivity PC Productivity PC Multimedia PC Multimedia PC Connected PC Connected PC Extended PC Extended PC
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Productivity PC Productivity PC
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Multimedia PC Multimedia PC
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Connected PC Connected PC
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Extended PC Extended PC
memory bandwidth requirements memory bandwidth requirements
100MB/sec
500MB/sec
3GB/sec
EDO DRAM
SDRAM
Main Memory BW
Time
RDRAM/
DDR
processor performance will continue processor performance will continue
to follow to follow Moores Moores law law
286 286
Intel386 CPU Intel386 CPU
Intel486CPU Intel486CPU
8088 8088
85 85 90 90 95 95 80 80
Relative processor Relative processor
Performance Performance
Pentium Pentium

II II
Processor Processor
Source: Intel Source: Intel
IntelDX2 IntelDX2- -50 50
00 00 05 05
Pentium Pentium

III III
Processor Processor
Pentium Pentium

4 4
Processor Processor
Pentium Pentium

Processor Processor
Pentium Pentium

Pro Pro
Processor Processor
processor performance will continue processor performance will continue
to follow to follow Moores Moores law law
286 286
Intel386 CPU Intel386 CPU
Intel486CPU Intel486CPU
8088 8088
85 85 90 90 95 95 80 80
Relative processor Relative processor
Performance Performance
Pentium Pentium

II II
Processor Processor
Source: Intel Source: Intel
IntelDX2 IntelDX2- -50 50
00 00 05 05
Pentium Pentium

III III
Processor Processor
Pentium Pentium

4 4
Processor Processor
Pentium Pentium

Processor Processor
Pentium Pentium

Pro Pro
Processor Processor
Will be new Industry Will be new Industry
Standard Standard
Interconnect Interconnect
ISA
EISA
MCA
VESA
PCI
PCI-X
HL
Others
AGP
1980s 1990s
PCI
Express
2000s
1 IO
(1GIO)
2 IO
(2GIO)
3 IO
(3GIO)
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P C IE x press
P C IE x press
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s P latform
s P latform
Local I/O
Local I/O
USB1.1 USB1.1
Graphics
Graphics
I/O
Bridge
I/O
Bridge
Memory
Bridge
Processor System Bus Processor System Bus
ATA ATA
AGP AGP
HubLink HubLink or others or others
PCI PCI
HDD
HDD
Memory
Memory
CPU

s P latform
s P latform
P entium- 4
8 2 8 4 5
MC H
8 2 8 0 1 B A
IC H 2
P C 1 3 3
D D R
A G P 4 X
P C I2 . 2
3 3 MH z / 3 2 - b it
L A N
F S B ( 4 0 0MH z )
U S B 1 . 1
A T A 1 0 0
8 5 0 ( E )
H ubI nterface
A C 9 7
P entium- 4
8 2 8 5 0 E
MC H
8 2 8 0 1 B A
IC H 2
3 0 0 ( 4 0 0 )
R D R A M
A G P 4 X
P C I2 . 2
3 3 MH z / 3 2 - b it
L A N
F S B ( 4 0 0 ( 5 3 3 )MH z )
U S B 1 . 1
A T A 1 0 0
H ubI nterface
A C 9 7
8 4 5

s P latform
s P latform
A th lon
7 5 1
( S y stem C ontroller)
7 5 6
( P eriph eral
B us C ontroller)
P C 1 0 0
S D R A M
A G P 2 X
P C I2 . 2
3 3 MH z / 3 2 - b it
IS A
K ey b oard
P S / 2Mouse
F S B ( 2 0 0 MH z )
U S B 1 . 0
7 5 0
A T A 6 6
A th lon
7 6 2
( S y stem C ontroller)
7 6 6 ( 7 6 8 )
( P eriph eral
B us C ontroller)
P C 1 3 3
D D R
A G P 4 X
P C I2 . 2
3 3 ( 6 6 ) MH z
3 2 / 6 4 - b it
A C 9 7
F S B
( 2 6 6 MH z )
U S B 1 . 1
7 6 0 MP ( MP X )
A T A 1 0 0
A th lon
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P C I
P C I
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X
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s V iew of th e P C IB us
s V iew of th e P C IB us

s V iew of th e P C IB us
s V iew of th e P C IB us
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Gb
Ethernet*
Gb
Ethernet*
Mobile
Docking
Mobile
Docking
Add ins
Add ins
USB2.0 USB2.0
Graphics
Graphics Memory
Bridge
Memory
Bridge
I/O
Bridge
I/O
Bridge
Serial ATA Serial ATA
3GIO 3GIO
3GIO 3GIO
PCI PCI
HDD
HDD
Memory
Memory
Switch
Switch
3GIO 3GIO
3GIO 3GIO
Local I/O
Local I/O
3GIO 3GIO
CPU
CPU
PCI
SATA
LPC
USB2
PCI-X
Bridge
Bridge
IBA
IBA
Chipset
Chipset
CPU
CPU
CPU
CPU
GbE
GbE
Bridge
Bridge
Memory
Memory
3GIO 3GIO
InfiniBand* InfiniBand*
3GIO 3GIO 3GIO 3GIO
InfiniBand*
Switched
Fabric
InfiniBand* InfiniBand*
Switched Switched
Fabric Fabric
CPU CPU
Chipset
Chipset
GbE
Switch
Memory
Memory
Memory
Memory
3GIO x 8 3GIO x 8
3GIO x 8 3GIO x 8
3GIO 3GIO
PCI
Bridge
PCI
Bridge
Line Line
Card Card
Line Line
Card Card
Line Line
Card Card
Line Line
Card Card
Line Line
Card Card
3GIO 3GIO
Layered architecture enables future expansion
Layered architecture enables future expansion
2.5+ Gb/s 2.5+ Gb/s
PCI PnP Model (init, enum, config) PCI PnP Model (init, enum, config)
PCI Software/Driver Model PCI Software/Driver Model
Data Integrity Data Integrity
Config/OS
S/W
Transaction
Data Link
Packet Packet- -based Protocol based Protocol
Physical
(electrical
Mechanical)
Point to point, serial, differential, Point to point, serial, differential,
hot hot- -plug, inter plug, inter- -op form factors op form factors
> > 2.5Gb/s/port/direction 2.5Gb/s/port/direction
Future speeds &
encoding
techniques only
impact the
Physical layer
No OS impact No OS impact
Transaction Layer
Transaction Layer
Data Link Layer
Data Link Layer
Physical Layer
Physical Layer
Data
Header CRC Frame
Packet
Sequence
Number
Frame
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Clock Clock
D
e
v
i
c
e

A
D
e
v
i
c
e

B
Selectable Width
Byte Stream
Byte Stream
{conceptual} {conceptual}
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
. . .
Byte 4
Byte 0
Byte 5
Byte 1
Byte 6
Byte 2
Byte 7
Byte 3
Lane 0 Lane 0
8b/10b
P > S
Lane 1 Lane 1
8b/10b
P > S
Lane 2 Lane 2
8b/10b
P > S
Lane 3 Lane 3
8b/10b
P > S
Lane 0 Lane 0
8b/10b
P > S
Byte 2
Byte 3
Byte 1
Byte 0
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
. . .
Band
Band
width is selectable
width is selectable
using
using
multiple lanes
multiple lanes
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B
W
/
P
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M
B
/
s
B
W
/
P
i
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M
B
/
s
0.00
20.00
40.00
60.00
80.00
100.00
BW/pin
1.58 7.09 9.85 11.57 26.60 100
PCI PCI-X AGP4X HL1 HL2 3GIO

Low
Low

bandwidth concept
bandwidth concept
Existing PCI Connector
3GIO Connector

H ig h
H ig h

bandwidth concept
bandwidth concept
Todays Add-in Card
with large connector
Example: Mini-3GIO
BTO/CTO Add-in
Card with wired
functionality

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