EXPERIMENT NO :-5

Ramniwas Date:-21/10/2013
2012uec1459 Batch:-EC-3

1. Aim:-
To verify the operation of full 4 bit parity generator and checker.
2. Boolean Experation:-
Input parity bit


Output parity bit


3. Circuit Diagram:- To generate input parity

To check output parity

4. Truth Table:-

5. K Map:-
For input ODD parity bit

For input EVEN parity bit

6. IC used:-
IC 7486




IC 7404

7. Result :-
performed the operation of 4 bit parity generator and checker using truth table.
8. Conclusion:-
In a digital data transfer system to detect error a parity bit is employed using
parity generator. Parity generator generate even and odd parity bit. Even parity bit makes no of
ones even and odd parity bit makes no of ones odd. Input odd parity bit is compliment of
input even parity bit. If output parity is 0 than there is no error otherwise error is present.