LITERATURE SURVEY

L. Ciminiera and A. Valenzano, "Low cost serial multipliers for high speed specialised
processors," Computers and Digital Techniques, IEEProc. E, vol. 135.5, 1988, pp. 259-265.

INTRODUCTION:
In digital system such as signal processing, pattern recognition, image processing are
need for high speed fixed and floating point computations. In this paper the two main
requirements are exploiting the intrinsic parallelism of these structures are the simplicity of the
basic cell organization, and the regularity of both the resulting array and the inter-cell data
transfer paths. The data lines are connecting in adjacent cells are often a serious drawback to the
implementation of the overall array architecture, since large chip areas must be devoted to the
input/output signals which connect the different units. Four new arrays are introduced for signed
number multiplication and multiplication/ addition. Two arrays operate in serial-parallel and
other two arrays operate in fully serial. The arithmetic units which is used as a basic blocks of
special processors perform functions as non-recursive digital filtering, signal correlation and
matrix multiplication.
KEYWORDS:
Serial-parallel multiplication, fully serial multiplication, serial-parallel arrays,
serial-serial arrays.
SUMMARY:
Two arrays are present in this paper are mainly used to obtain low-cost implementation
of single unit. So the whole processor could be implement in limited number of chips. The
arithmetic arrays are suited for implementation of specialized arithmetic processor such as
systolic arrays. Multiplication and addition operations are considered for large set of complex
arithmetic algorithms such as matrix multiplication, inner product computation, signal filtering
and FFT computation. The cost evaluation of MIAD(multi-input adder) leads to a gate count of
78 per cell, with a total of n cells, while, in the first two arrays presented, the basic cell is
implemented with a maximum 24 gates, with a number of cells of n - 1 + 0.5. The speed can be
achieved by redundant representations for the results, with a cost equivalent to their counterparts
based on full 2s complement representation.

LIMITATION:
Serialparallel multiplication/addition increases area and power.