4-Bit Ripple Adder

Hisham Alshafi
Lab date: 9/4/14
Due 9/8/14 ITCS
3181L Fall 2014










Purpose:
The purpose is to create a 4-bit adder by implementing the
logical components (AND, OR, NOT, XOR). The report will
include the 1-Bit and 4-Bit adders along with schematics and
logical components used



Analysis:
First, we create the logical components along with
schematic and symbol for each one (AND, OR, NOT). Second,
we create logical component XOR with schematic and symbol
and use that to create 1-bit adder then 4-bit adder.





4 Bit Ripple Adder:
Schematic



Symbol





Command File




Expected Results
C A0 A1 A2 A3 B0 B1 B2 B3 COUT S0 S1 S2 S3
0 1 0 1 1 0 1 0 0 0 1 1 1 1
0 0 1 0 1 1 0 0 0 0 1 1 0 1
0 1 1 0 1 1 0 0 0 0 0 1 0 1
0 0 0 0 1 0 1 0 0 0 1 1 0 1
0 1 0 0 1 0 1 0 0 0 1 1 0 1
0 0 0 0 1 0 1 0 0 0 0 1 0 1
0 1 0 0 1 0 1 0 0 0 1 1 0 1
0 0 1 0 1 1 1 0 0 0 1 0 0 1
0 1 1 0 1 1 1 0 0 0 0 0 0 1
0 0 1 0 1 1 1 0 0 0 1 0 0 1
0 1 1 0 1 1 1 0 0 0 0 0 0 1




Simulation Result (Built-in)

Simulation Result (Real-Time)






1 Bit Adder
Schematic


Symbol


Command File


Expected Results
A B CIN COUT S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

Simulation Result (Built-in)

Simulation Result (Real-Time)


XOR Gate
Schematic


Symbol





Command File



Expected results:
A B Q
0 0 0
0 1 1
1 0 1
1 1 0

Simulation Result (Built-in)

Simulation Result (Real-Time)




AND Gate
Schematic (built in and Motorola libraries)


Symbol


Command File


Expected results
A B Q
0 0 0
0 1 0
1 0 0
1 1 1

Simulation Result (Built-in)


Simulation Result (Real-Time)





OR Gate
Schematic (built in and Motorola libraries)



Symbol


Command File


Expected results
A B Q
0 0 0
0 1 1
1 0 1
1 1 1

Simulation Result (Built-in)

Simulation Result (Real-Time)





NOT Gate
Schematic (built in and Motorola libraries)


Symbol



Command File


Expected Result:
A Q
0 1
1 0

Simulation result (Built-in)



Simulation result (Real-Time)