EE214 - Digital Circuits Lab 2

Priyanshu Gupta
Roll Number: 210070064
August 16, 2022

Contents
1 Part-A: 4 to 2 encoder 2
1.1 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1.1 Pen & Paper design . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1.2 Code file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Observation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Part-B: 4 to 2 priority encoder 4

2.1 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.1 Pen & Paper design . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.2 Code file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Observation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Part-C: 8 to 3 encoder 7
3.1 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.1 Pen & Paper design . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.2 Code file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Observation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1
Overview
Lab-2 was about designing logic for encoders using structural modelling and simulate
it using ModelSim and VHDL as the language.

1 Part-A: 4 to 2 encoder
1.1 Setup
We will be designing logic for 4 to 2 encoder with enable input.
The truth table for 4 to 2 encoder is:

A B C D En Y1 Y0
0 0 0 1 0 0 0
0 0 0 1 1 0 0
0 0 1 0 0 0 0
0 0 1 0 1 0 1
0 1 0 0 0 0 0
0 1 0 0 1 1 0
1 0 0 0 0 0 0
Table 1: Truth Table for 4 to 2 encoder

The Logic for the outputs are:

Y1 = B · En + A · En

Y0 = C · En + A · En

1.1.1 Pen & Paper design

This is the pen and paper design I came up with for 4 to 2 encoder.

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 Figure 1: 4 to 2 encoder design

1.1.2 Code file

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.Gates.all;

entity Encoder is
port (input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(1 downto 0));
end entity Encoder;

architecture Model of Encoder is

signal Z1, Z2 : std_logic;
begin
OR1 : OR_2 port map(A=> input(4), B=> input(3), Y=> Z1);
OR2 : OR_2 port map(A=> input(4), B=> input(2), Y=> Z2);
AND1: AND_2 port map(A=> Z1, B=> input(0), Y=> output(1));
AND2: AND_2 port map(A=> Z2, B=> input(0), Y=> output(0));
end Model;

1.2 Observation
We can see that the RTL simulation gives the correct result as compared to the truth
table.

3
 Figure 2: RTL simulatioon of 4 to 2 encoder

2 Part-B: 4 to 2 priority encoder

2.1 Setup
We will be designing logic for 4 to 2 priority encoder with valid output.
The truth Table for 4 to 2 priority encoder is: The logic for 4 to 2 priority encoder is:

A B C D Y1 Y0 V
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 0 0 1 1
0 0 1 1 0 1 1
0 1 0 0 1 0 1
0 1 0 1 1 0 1
0 1 1 0 1 0 1
0 1 1 1 1 0 1
1 0 0 0 1 1 1
1 0 0 1 1 1 1
1 0 1 0 1 1 1
1 0 1 1 1 1 1
1 1 0 0 1 1 1
1 1 0 1 1 1 1
1 1 1 0 1 1 1
1 1 1 1 1 1 1
Table 2: Truth Table for 4 to 2 priority encoder

4
 Y1 = A + B

Y0 = A + B̄ · C
V =A+B+C +D

2.1.1 Pen & Paper design

This is the pen and paper design I came up with for 4 to 2 priority encoder.

Figure 3: Pen and paper desgin for 4 to 2 priority encoder

2.1.2 Code file

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.Gates.all;

entity P_Encoder is
port(input: in std_logic_vector(3 downto 0);
output: out std_logic_vector(2 downto 0));
end entity P_Encoder;

architecture Model1 of P_Encoder is

signal Z1, Z2, Z3, B0: std_logic;

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begin
INV: INVERTER port map(input(2),B0);
AND1: AND_2 port map(input(1),B0,Z3);
OR1: OR_2 port map(input(3), Z3, output(1));
OR2: OR_2 port map(input(3), input(2), output(2));
OR3: OR_2 port map(input(3), input(2), Z1);
OR4: OR_2 port map(input(1), input(0), Z2);
OR5: OR_2 port map(Z1, Z2, output(0));
end Model1;

2.2 Observation
We can see that RTL simulation gives the correct results as compared to the truth
table.

Figure 4: RTL simulation for 4 to 2 priority encoder

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3 Part-C: 8 to 3 encoder
3.1 Setup
We will be designing logic 8 to 3 encoder using 4 to 2 encoders designed before and
only OR gates.
Truth Table for 8 to 3 encoder is :

Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 E A2 A1 A0
0 0 0 0 0 0 0 1 0 0 0 0
0 0 0 0 0 0 0 1 1 0 0 0
0 0 0 0 0 0 1 0 0 0 0 0
0 0 0 0 0 0 1 0 1 0 0 1
0 0 0 0 0 1 0 0 0 0 0 0
0 0 0 0 0 1 0 0 1 0 1 0
0 0 0 0 1 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 1 0 1 1
0 0 0 1 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 1 1 0 0
0 0 1 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 1 1 0 1
0 1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 1 1 1 0
1 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 1 1 1 1
Table 3: Caption

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3.1.1 Pen & Paper design
This is the pen and paper design i came up with for 8 to 2 encoder:

3.1.2 Code file

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.Gates.all;

entity Encoder_8to3 is
port (inp: in std_logic_vector(8 downto 0);
outp: out std_logic_vector(2 downto 0));
end entity;

architecture Model of Encoder_8to3 is

signal S1, S0, S2, S3, Z1, Z2, Z3: std_logic;

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signal T1: std_logic_vector(4 downto 0) ;
signal T2: std_logic_vector(4 downto 0) ;

component Encoder is
port (input: in std_logic_vector(4 downto 0);
output: out std_logic_vector(1 downto 0));
end component;
begin
T1 <= inp(8)& inp(7)& inp(6)& inp(5)& inp(0);
T2 <= inp(5) & ’0’ & ’0’ & ’0’ & inp(0);
ENC1: Encoder port map(inp(4 downto 0), output(1)=>S1, output(0)=>S0);
ENC2: Encoder port map(T1, output(1)=>S3, output(0)=>S2);
OR1: OR_2 port map(S0, S2, outp(0));
OR2: OR_2 port map(S1, S3, outp(1));
ENC3 : Encoder port map(T2, output(1)=>Z2, output(0)=>Z1);
OR3: OR_2 port map(S2, S3, Z3);
OR4: OR_2 port map(Z2, Z3, outp(2));
end Model;

3.2 Observation
We can see that RTL simulation gives the correct results as compared to the truth
table.

Figure 5: RTL simulation for 8 to 3 encoder