Baker/Saxena

High Speed Op-amp Design: Compensation and

Topologies for Two and Three Stage Designs
R. Jacob Baker and Vishal Saxena
Department of Electrical and Computer Engineering
Boise State University
1910 University Dr., MEC 108
Boise, ID 83725
jbaker@boisestate.edu and vishalsaxena@ieee.org
Abstract :
As CMOS technology continues to evolve, the supply voltages are decreasing while at
the same time the transistor threshold voltages are remaining relatively constant. Making
matters worse, the inherent gain available from the nano-CMOS transistors is dropping.
Traditional techniques for achieving high gain by vertically stacking (i.e. cascoding)
transistors becomes less useful in sub-100nm processes. Horizontal cascading (multi-
stage) must be used in order to realize op-amps in low supply voltage processes.
This seminar discusses new design techniques for the realization of multi-stage op-amps.
Both single- and fully-differential op-amps are presented where low power, small
VDD, and high speed are important. The proposed, and experimentally verified, op-
amps exhibit significant improvements in speed over the traditional op-amp designs
while at the same time having smaller layout area.
Baker/Saxena
Outline
Introduction
Two-stage Op-amp Compensation
Multi-stage Op-amp Design
Multi-stage Fully-Differential Op-amps
Conclusion
Baker/Saxena
Op-amps and CMOS Scaling
The Operational Amplifier (op-amp) is a fundamental building
block in Mixed Signal design.
Employed profusely in data converters, filters, sensors, drivers etc.
Continued scaling in CMOS technology has been challenging
the established paradigms for op-amp design.
With downscaling in channel length (L)
Transition frequency increases (more speed).
Open-loop gain reduces (lower gains).
Supply voltage is scaled down (lower headroom) [1].
Baker/Saxena
CMOS Scaling Trends
VDD is scaling down but V
THN
is almost constant.
Design headroom is shrinking faster.
Transistor open-loop gain is dropping (~10s in nano-CMOS)
Results in lower op-amp open-loop gain. But we need gain!
Random offsets due to device mismatches.
[3], [4].
Baker/Saxena
Integration of Analog into Nano-CMOS?
Design low-VDD op-amps.
Replace vertical stacking (cascoding) by horizontal cascading of gain
stages (see the next slide).
Explore more effective op-amp compensation techniques.
Offset tolerant designs.
Also minimize power and layout area to keep up with the
digital trend.
Better power supply noise rejection (PSRR).
Baker/Saxena
Cascoding vs Cascading in Op-amps
A Telescopic Two-stage Op-amp
A Cascade of low-VDD
Amplifier Blocks.
(Compensation not shown here)
1
VDD VDD
Vbiasn
vp vm
VDD
CL
vout
2
VDD VDD
Vbiasn
VDD VDD
Vbiasn
n-1
n
Stage 1 Stage 2 Stage (n-1) Stage n
VDD
min
>4V
ovn
+V
ovp
+V
THP
with
wide-swing biasing. [1]
VDD
min
=2V
ovn
+V
ovp
+V
THP.
Even if we employ wide-swing biasing for low-voltage designs, three- or
higher stage op-amps will be indispensable in realizing large open-loop DC
gain.
Baker/Saxena
TWO-STAGE OP-AMP COMPENSATION
Baker/Saxena
Direct (or Miller) Compensation
1
2
v
m
v
p
v
out
V
bias4
V
bias3
C
C
10pF
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2.
VDD VDD
VDD
30pF
C
L
M3 M4
M1 M2
M6TL
M6BL
M6TR
M6BR
M8T
M8B
M7
220/2
100/2
100/2
x10
750
i
C
fb
i
C
ff
Compensation capacitor (C
c
)
between the output of the gain stages
causes pole-splitting and achieves
dominant pole compensation.
An RHP zero exists at
Due to feed-forward component of
the compensation current (i
C
).
The second pole is located at
The unity-gain frequency is
All the op-amps presented have been designed in AMI C5N 0.5m CMOS process with scale=0.3 m and L
min
=2.
The op-amps drive a 30pF off-chip load offered by the test-setup.
Baker/Saxena
Drawbacks of Direct (Miller) Compensation
The RHP zero decreases phase
margin
Requires large C
C
for
compensation (10pF here for a
30pF load!).
Slow-speed for a given load, C
L.
Poor PSRR
Supply noise feeds to the output
through C
C
.
Large layout size.
1
2
v
m
v
p
v
out
V
bias4
V
bias3
C
C
10pF
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2.
VDD VDD
VDD
30pF
C
L
M3 M4
M1 M2
M6TL
M6BL
M6TR
M6BR
M8T
M8B
M7
220/2
100/2
100/2
x10
Baker/Saxena
Indirect Compensation
The RHP zero can be eliminated by
blocking the feed-forward compensation
current component by using
A common gate stage,
A voltage buffer,
Common gate embedded in the
cascode diff-amp, or
A current mirror buffer.
Now, the compensation current is fed-
back from the output to node-1 indirectly
through a low-Z node-A.
Since node-1 is not loaded by C
C
, this
results in higher unity-gain frequency
(f
un
).
An indirect-compensated op-amp
using a common-gate stage.
1
2
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2.
VDD VDD
VDD
30pF
220/2
100/2
100/2
x10
VDD
V
bias3
V
bias4
v
m
v
p
v
out
C
c
C
L
i
c
M
CG
A
M3 M4
M1
M6TL
M6BL
M6TR
M6BR
M8T
M8B
M7
M2
M9
M10T
M10B
Baker/Saxena
Indirect Compensation in a Cascoded Op-amp
1
2
v
m
v
p
v
out
C
C
1.5pF
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 44/2.
VDD VDD
VDD
30pF
C
L
V
bias2
V
bias3
V
bias4
A
50/2
50/2
110/2
M1 M2
M6TL
M6BL
M6TR
M6BR
M3T
M3B
M4T
M4B
M8T
M8B
M7
i
c
Indirect-compensation using
cascoded current mirror load.
v
m
v
p
v
out
C
C
C
L
Indirect-compensation using
cascoded diff-pair.
Employing the common gate device embedded in the cascode structure
for indirect compensation avoids a separate buffer stage.
Lower power consumption.
Also voltage buffer reduces the swing which is avoided here.
Baker/Saxena
Analytical Modeling of Indirect Compensation
Block Diagram
Small signal analytical model
R
C
is the resistance
attached to node-A.
i
c
v
out
sC
c
R
c

+ 1
The compensation
current (i
C
) is indirectly
fed-back to node-1.
Baker/Saxena
Derivation of the Small-Signal Model
The small-signal model
for a common gate
indirect compensated op-
amp topology is
approximated to the
simplified model seen in
the last slide.
Resistance r
oc
is
assumed to be large.
g
mc
>>r
oc
-1
, R
A
-1
,
C
C
>>C
A
Baker/Saxena
Analytical Results for Indirect Compensation
j

z
1

un
p
1
p
2
p
3
Pole-zero plot
Pole p
2
is much farther away from f
un
.
Can use smaller g
m2
=>less power!
LHP zero improves phase margin.
Much faster op-amp with lower
power and smaller C
C
.
Better slew rate as C
C
is smaller.
LHP zero
Baker/Saxena
Indirect Compensation Using Split-Length Devices
As VDD scales down, cascoding is becoming tough. Then how to realize
indirect compensation as we have no low-Z node available?
Solution: Employ split-length devices to create a low-Z node.
Creates a pseudo-cascode stack but its really a single device.
In the NMOS case, the lower device is always in triode hence node-A is a
low-Z node. Similarly for the PMOS, node-A is low-Z.
NMOS PMOS
Split-length 44/4(=22/2)
PMOS layout
Baker/Saxena
Split-Length Current Mirror Load (SLCL) Op-amp
1
2
v
m
v
p
v
out
V
bias4
V
bias3
C
C
2pF
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2.
VDD VDD
VDD
30pF
C
L
M3B M4B
M1 M2
M6TL
M6BL
M6TR
M6BR
M8T
M8B
M7T
M3T
M4T
M7B
50/2
50/2
220/2
220/2
A
i
c
The current mirror load devices are
split-length to create low-Z node-A.
Here, f
un
=20MHz, PM=75 and
t
s
=60ns.
t
s
Frequency Response
Small step-input settling in follower
configuration
Baker/Saxena
SLCL Op-amp Analysis
1
2
v
out
A
1
g
mp
i
d1
i
d2
v
s
2
1
g
mp
g
m
v
s 1
2
+
-

v
s
2
C
L
C
c
v=0
1
2
v
out
A
1
g
mp
i
d1
v
s
2
C
L
C
c

g
g
v
m
mp
s
1
(a) (b)
+
-
+
-
1 2
g
m2
v
1
R
1
C
1
v
out
C
c
v
1
r
op
C
A
+
-
v
sgA
C
2 R
2
A

g
g
v
m
mp
s
1
1
g
mp
g
mp
v
sgA
i
c
v
out
sC
c
g
mp

+
1 1
+
-
+
-
1 2
g
m2
v
1 R
1
C
1
v
out
C
c
v
1
C
2 R
2 i
c
g
m
v
s 1 1
g
mp
g
m
v
s 1
2
1
g
mp
Here f
z1
=3.77f
un
LHP zero appears at a higher
frequency than f
un
.
Baker/Saxena
Split-Length Diff-Pair (SLDP) Op-amp
The diff-pair devices are split-length to
create low-Z node-A.
Here, f
un
=35MHz, PM=62, t
s
=75ns.
Better PSRR due to isolation of node-A
from the supply rails.
Frequency Response
Small step-input settling in follower
configuration
1
2
v
m
v
p
v
out
V
bias4
V
bias3
C
C
2pF
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2.
VDD VDD
VDD
30pF
C
L
M3 M4
M1B
M2B
M6TL
M6BL
M6TR
M6BR
M8T
M8B
M7
M1T
M2T
20/2
20/2
20/2
20/2
i
c
110/2
50/2
50/2
A
Baker/Saxena
SLDP Op-amp Analysis
v
out
v
s
2

v
s
2
1
g
mn
1
g
mn
v
out
v
s
2
1
g
mn
i
d
g
mn
v
s
2
4
=
Here f
z1
=0.94f
un
,
LHP zero appears slightly before
f
un
and flattens the magnitude
response.
This may degrade the phase
margin.
Not as good as SLCL, but is of
great utility in multi-stage op-amp
design due to higher PSRR.
+
-
+
-
1
2
g
m2
v
1 C
A
v
out
v
A
r
on
C
1
+
-
v
gs1
C
2 R
2
A
g
mn
v
gs1
v
s
2
1
g
mn
R
1 g
mn
v
s
4
C
c
1
g
mn
i
c
v
out
sC
c
g
mn

+
1 1
+
-
+
-
1 2
g
m2
v
1 R
1
C
1
v
out
C
c
v
1
C
2 R
2 i
c
g
mn
v
s
2
1
g
mn
Baker/Saxena
Test Chip 1: Two-stage Op-amps
Miller
3-Stage Indirect
SLCL
Indirect
SLDP
Indirect
Miller with Rz
AMI C5N 0.5m CMOS, 1.5mmX1.5mm die size.
Baker/Saxena
Test Results and Performance Comparison
Miller with Rz (t
s
=250ns)
SLCL Indirect (t
s
=60ns)
SLDP Indirect (t
s
=75ns)
Performance comparison of the op-amps for C
L
=30pF.
10X gain bandwidth (f
un
).
4X faster settling time.
55% smaller layout area.
40% less power consumption.
Baker/Saxena
MULTI-STAGE OP-AMP DESIGN
Baker/Saxena
Three-Stage Op-amps
Higher gain can be achieved by
cascading three gain stages.
~100dB in 0.5m CMOS
Results in at least a third order
system
3 poles and two zeros.
RHP zero(s) degrade the phase
margin.
Hard to compensate and stabilize.
Large power consumption compared
to the two-stage op-amps.
j

un
Pole-zero plot
Baker/Saxena
Biasing of Multi-Stage Op-amps
Diff-amps should be
employed in inner gain stages
to properly bias second and
third gain stages
Current in third stage is
precisely set.
Robust against large offsets.
Boosts the CMRR of the op-
amp (needed).
Common source second stage
should be avoided.
Will work in feedback
configuration but will have
offsets in nano-CMOS
processes.
Robust Biasing
Fallible Biasing
Baker/Saxena
Conventional Three-Stage Topologies
Requires p
3
=2p
2
=4
un
for stability
(Butterworth response)
Huge power consumption
RHP zero appears before the LHP
zero and degrades the phase
margin.
Second stage is non-inverting
Implemented using a current
mirror.
Excess forward path delay (not
modeled or discussed in the
literature).
Nested Miller Compensation (NMC) [6]
Baker/Saxena
Conventional Three-Stage Topologies contd.
Employs feed-forward g
m
s to
eliminate zeros.
g
mf1
=g
m1
and g
mf2
=g
m2
Class AB output stage.
Hard to implement g
mf1
which
tracks g
m1
for large signal swings.
Also wasteful of power.
g
mf2
is a power device and will not
always be equal to g
m2
.
Compensation breaks down.
Still consumes large power.
Nested Gm-C Compensation (NGCC) [7]
Baker/Saxena
Conventional Three-Stage Topologies contd.
Four poles and double LHP zeros
One LHP zero z
1
cancels the pole p
3.
Other LHP zero z
2
enhances phase
margin.
Set p
2
=2
un
for PM=60.
Relatively low power.
Still design criterions are complex.
Complicated bias circuit.
More power.
Excess forward path delay.
Transconductance with Capacitive
Feedback Compensation (TCFC) [14]
1
2
VDD VDD VDD VDD VDD VDD
v
m
v
p
v
out
C
C2
V
B1
V
B3
V
B7
V
B2
g
m1
g
m3
3
g
m2
/2
g
mf
V
B4
V
B5
1:2
V
B6
g
mt
C
C1
Baker/Saxena
Three-Stage Topologies: Latest in the literature
Employs reverse nesting of
compensation capacitors
Since output is only loaded by only
C
C2
, results in potentially higher f
un
.
Third stage is always non-inverting.
Uses pole-zero cancellation to realize
higher phase margins.
Excess forward path delay.
Biasing not robust against process
variations. How do you control the
current in the output buffer?
Reverse Nested Miller with Voltage Buffer
and Resistance (RNMC-VBR) [8]
1
VDD
v
m v
p
g
m1
VDD
20uA
2
3
VDD VDD VDD VDD
v
out
C
L
C
c1
C
c2
g
m2
g
m3
g
mf
g
mVB
R
C1
Baker/Saxena
Three-Stage Topologies: Latest in the literature contd.
Reversed nested with elimination of
RHP zero.
High gain block (HGB) realizes gain
by cascading stages.
High speed block (HSB) implements
compensation at high frequencies.
Complex design criterions.
Excess forward path delay. Again,
uses a non-inverting gain stage.
Employs a complicated bias circuit.
More power consumption.
Active Feedback Frequency
Compensation (AFFC) [9]
-A
1
+A
2
C
a
1
2
v
s v
out
-A
3
3
C
m
-g
mf
+g
ma
High-Gain Block (HGB)
High-Speed Block (HSB)
Input Block
Baker/Saxena
Three-Stage Topologies: Latest in the literature contd.
Various topologies have been recently reported by combining the earlier
techniques.
RNMC feed-forward with nulling resistor (RNMCFNR) [17].
Reverse active feedback frequency compensation (RAFFC) [17].
Further improvements are required in
Eliminating excess forward path delay arising due to the compulsory non-
inverting stages.
Robust biasing against random offsets in nano-CMOS.
Further reduction in power and circuit complexity.
Better PSRR.
Baker/Saxena
Indirect Compensation in Three-Stage Op-amps
Indirectly feedback the compensation
currents i
c1
and i
c2
.
Reversed Nested
Thus named RNIC.
Employ diff-amp stages for robust
biasing and higher CMRR.
Use SLDP for higher PSRR.
Minimum forward path delay.
No compulsion on the polarity of gain
stages.
Can realize any permutation of stage
polarities by just changing the sign of
the fed-back compensation current
using fbr and fbl nodes.
Low-voltage design.
Note Class A (well modify after
theory is discussed).
VDD VDD
VDD
V
biasn
v
p
fbl
fbr
C
c2
C
L
v
m
VDD VDD
v
out C
c1
fbl
fbr
+ve
-ve
i
c1
i
c2
1
2
3
Baker/Saxena
Indirect Compensation in Three-Stage Op-amps contd.
VDD VDD
VDD
V
biasn
v
p
fbl
fbr
C
c2
C
L
v
m
VDD VDD
v
out C
c1
fbl
fbr
+ve
-ve
i
c1
i
c2
1
2
3
Note the red arrows showing the node movements and the signs of the
compensation currents.
fbr and fbl are the low-Z nodes used for indirect compensation (have
resistances R
c1
and R
c2
attached to them).
The C
C
s are connected across two-nodes which move in opposite direction
for overall negative feedback the compensation loops.
Note feedback and forward delays!
Baker/Saxena
Analysis of the Indirect Compensated 3-Stage Op-amp
i
v
sCc R
c
c
1
2
1 1
1

+
i
v
sC R
c
out
c c
2
2 2
1

+
Two LHP zeros
Four non-dominant poles.
Plug in the indirect compensation model developed for the two-stage op-
amps.
Baker/Saxena
Pole-zero Cancellation
Poles p
4,5
are parasitic conjugated poles located far away in frequency.
Appear due to the loading of the nodes fbr and fbl.
The small signal transfer function can be written as
The quadratic expression in the denominator describing the poles p
2
and p
3
can be canceled by the numerator which describes the LHP zeros.
Results in LHP zeros z
1
and z
2
canceling the poles p
2
and p
3
resp.
The resulting expression looks like a single pole system for low
frequencies. Phase margin close to 90.
Baker/Saxena
Pole-zero Cancellation contd.
j

un
Design Equations
Place pole-zero doublets (p
2
-z
1
and p
3
-
z
2
) out of f
un
for clean transients.
i.e. f
p2
, f
p3
> f
un
.
Best possible pole-zero arrangement
for low power design.
Results into design equations
independent of parasitics (C
3
C
L
here).
R
c1
and R
c2
are realized by adding poly
Rs in series with C
C1
and C
C2
.
Also R
c1
, R
c2
R
c0
, the impedance
attached to the low-Z nodes fbr/fbl.
Robust against even 50% process
variations in Rs and Cs as long as the
pole-zero doublets stay out of f
un
.
Baker/Saxena
Pole-zero cancelled Class-A Op-amp
A Here, the poly resistors are estimated as
Low power, simple, robust and manufacturable topology*.
The presented three-stage op-amps have been designed with transient and SR performances to
be comparable to their two-stage counterparts.
Baker/Saxena
Pole-zero cancelled Class-AB Op-amp 1
A dual-gain path, low-power Class-AB op-amp topology (RNIC-1).
The design equation for R
c1
is modified as
Baker/Saxena
Pole-zero cancelled Class-AB Op-amp 2
A single-gain path, Class-AB op-amp topology for good THD
performance.
Floating current source for biasing the output buffer.
Here, V
ncas
= 2V
GS
and V
pcas
=VDD 2V
SG
.
Note the lack of gratuitous forward delay.
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2.
VDD VDD
VDD
30pF
20/2
20/2
20/2
20/2
V
biasn
v
p
fbl
fbr
220/2
100/2
C
L
v
m
VDD VDD
v
out
1
2
3
M4 M5
M1T
M1B
M2T
M2B
M3L M3R M7L M7R
M8 M9
M5 M6
M10
M11
V
biasp
66/2 66/2
V
biasn
VDD
V
pcas
V
ncas
10/2
11/2
MFCP
MFCN C
c1
fbl
R
1c
C
c2
fbr
R
2c
7.65K
4.08K
1p
2p
Baker/Saxena
Simulation of Three-stage Op-amps
-150
-100
-50
0
50
100
M
a
g
n
i
t
u
d
e

(
d
B
)
10
2
10
4
10
6
10
8
10
10
-225
-180
-135
-90
-45
0
P
h
a
s
e

(
d
e
g
)
Bode Diagram
Frequency (Hz)
Analytical model of the Class-AB (RNIC-1) topology is simulated in
MATLAB.
The pole-zero plot illustrates the double pole-zero cancelation (collocation).
p
4
and p
5
are parasitic poles located at frequencies close to that of the f
T
limited
(or mirror) poles.
Here, fun30MHz and PM=90 for C
L
=30pF.
Baker/Saxena
Simulation of Three-stage Op-amps contd.
SPICE simulation of the same Class AB op-amp.
C
L
=30pF: f
un
=30MHz, PM88, t
s
=70ns, 0.84mW, SR=20V/s.
As fast as a two-stage op-amp with only 20% more power, at 50% VDD and with
the same layout area (simpler bias circuit).
Operates at VDD as low as 1.25V in a 5V process (25% of V
DD
).
SPICE simulation match with the MATLAB simulation
Our theory for three-stage indirect compensation is validated.
Baker/Saxena
Chip 2: Low-VDD 3-Stage Op-amps
Best
Performance
AMI C5N 0.5m CMOS, 1.5mmX1.5mm die size.
Baker/Saxena
Performance Comparison
Figures of Merit
FoM
S
=f
un
C
L
/Power
FoM
L
=SR.C
L
/Power
IFoM
S
=f
un
C
L
/I
DD
IFoM
L
=SR.C
L
/I
DD
RNIC op-amp designed
for 500pF load for a fair
comparison.
FoMs>2X than state-of-
the-art at V
DD
=3V.
Comparable performance
even at lower V
DD
=2V.
Practical, stable and
production worthy.
Baker/Saxena
Performance Comparison contd.
0
10000
20000
30000
40000
50000
60000
M
N
M
C
N
G
C
C
N
M
C
F
N
R
D
F
C
F
C
A
F
F
C
A
C
B
C
F
T
C
F
C
D
P
Z
C
F
R
N
M
C

V
B

N
R
S
M
F
F
C
R
N
M
C
F
N
R
R
A
F
F
C
R
A
F
F
C

L
P
R
N
I
C
-
2

(
T
h
i
s

w
o
r
k
)
R
N
I
C
-
3

(
T
h
i
s

w
o
r
k
)
R
N
I
C
-
2
A

(
T
h
is

w
o
r
k
)
R
N
I
C
-
3
A

(
T
h
is

w
o
r
k
)
FOM_S
FOM_L
IFOM_S
IFOM_L
Higher performance figures
than state-of-the-art.
10X faster settling.
Better phase margins.
Layout area same or smaller.
Baker/Saxena
Flowchart for RNIC Op-amp Design
Start with the initial
specifications on fun, CL,
Av, and SR.
Select the overdrive (% of
VDD) which will set VGS, fT
and transistor gain gm*ro.
Identify gm1. Can
initially set gm2 equal to
gm1 or a to lower value.
Select Cc2 = gm1/fun
Select Cc1 and gm3 such that
the p2-z1 and p3-z2 doublet
locations are outside fun.
Calculate R1c and R2c.
Is either of R1c
and R2c negative?
Are the parasitic
poles p4,5 degrading
PM by closing on
fun?
Simulate the design for
frequency response
and transient settling.
Does the design
meet the
specifications?
No
Lower
power?
Smaller
layout
area?
More
Speed?
Better SR?
Split DC gain AOLDC
across A1, A2 and A3.
Move the corresponding pi-zj
doublet to a lower frequency
by changing Cci and Rci. May
have to sacrifice fun.
Yes
End
Yes
Increase gm1 or
decrease Cc2.
Yes
No
Decrease gm3 or gm2.
In the worst case
scenario decrease
gm1.
Yes
No
Reduce Cc1, Cc2 or
gm3.
Yes
No
Increase bias current in the
first stage (i.e. ISS1) or use
smaller CCs
Yes
Nothing works!
Revisit biasing.
No
Increase gm2. Yes
No
No
Baker/Saxena
N-Stage Indirect Compensation Theory
C
c
1
C
c
2
C
c
n2
C
c
n1
i
c
1
i
c
2
i
c
n1
i
c
n2
The three-stage indirect compensation theory has been extended to N-
stages and the closed form small signal transfer function is obtained.
Baker/Saxena
MULTI-STAGE FULLY-DIFFERENTIAL
OP-AMPS
Baker/Saxena
Fully Differential Op-amps
Analog signal processing uses only
fully differential (FD) circuits.
Cancels switch non-linearities and even
order harmonics.
Double the dynamic range.
Needs additional circuitry to maintain
the output common-mode level.
Common-mode feedback circuit
(CMFB) is employed.
v
op
-v
om
=-A(v
inp
-v
inm
)
Baker/Saxena
Three-Stage FD Op-amp Design: Problems
The CMFB loop disturbs the DC biasing of the intermediate gain stages.
Degrades the gain, performance and may cause instability.
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2.
VDD VDD
20/2
20/2
20/2
20/2
Vbiasn
v
p
fbl
fbr
v
m
VDD
20/2
20/2
VCM
v
op1
v
om1
VCMFB1
VDD
v
om
Cc2
fbl
R2c
110/2
100/2
50/2
VCMFB3
VDD
VDD
v
op
Cc2
fbr
R2c
110/2
100/2
50/2
VDD
VCM
3
0
K
1
0
0
f
3
0
K
1
0
0
f
v
om
v
op
VCM
VCMFB1
v
op2
v
om2
First Stage Second Stage
Output Buffer
(Third Stage)
100/2 100/2
Cc1
VDD VDD
Vbiasn
VDD
v
op2
v
om2
R1c
fbr fbl
R1c
v
op1 v
om1 Vbiasp
Cc1
VDD
Block Diagram Circuit Implementation
Baker/Saxena
Three-Stage FD Op-amp Design: Solutions
-A
1
+A
2
C
c1
vp
v
op
-A
3
C
c2
-
+
1
p
2
p 3p
-A
1 +A
2
C
c1
v
m
v
om
-A
3
C
c2
-
+
1
m
2
m
3m
vCM vbiasn vbiasp
-A
1
+A
2
C
c1
v
p
v
op
-A
3
C
c2
-
+
1
p
2
p 3
p
-A
1 +A
2
C
c1
v
m
v
om
-A
3
C
c2
-
+
1
m
2
m
3
m
v
CM
v
CMFB
-A
1
+A
2
C
c1
v
p
v
op
-A
3
C
c2
-
+
1
p
2
p 3
p
-A
1 +A
2
C
c1
v
m
v
om
-A
3
C
c2
-
+
1
m
2
m
3
m
v
CM
v
CMFB
Employ CMFB
1. Individually across all the stages.
2. Only across the last two stages as the
biasing of the output buffer need not be
precise.
3. Only in the third stage (output buffer).
1.
2.
3.
Baker/Saxena
Three-Stage FD Op-amp Design
VDD VDD
20/2
20/2
20/2
20/2
Vbiasn
v
p
fbl
fbr
v
m
VDD
20/2
20/2
VCM
v
op1
v
om1
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2.
3
0
K
1
0
0
f
3
0
K
1
0
0
f
v
om
v
op
VCM
VCMFB3
VDD VDD
Vbiasn
v
op2
VDD VDD
Vbiasn
v
om2
Cc1
fbl
R1c
Cc1
fbr
R1c
First Gain Stage
Second Gain Stage
VDD
v
om
Cc2
fbl
R2c
110/2
100/2
50/2
VCMFB3
VDD
VDD
v
op
Cc2
fbr
R2c
110/2
100/2
50/2
VDD
VCM
v
op2
v
om2
Output Buffer
(Third Stage)
100/2 100/2
Use CMFB only in the output (third) stage. Manufacturable design.
Leaves the biasing of second and third stage alone without disturbing them.
Employ diff-amp pairs in the second stage for robust biasing.
Block Diagram
Circuit Implementation
Baker/Saxena
Three-Stage FD Op-amp: Enlarged
3
0
K
1
0
0
f
3
0
K
1
0
0
f
Baker/Saxena
Chip 3: Low-VDD FD Op-amps
Best
Performance
AMI C5N 0.5m CMOS, 1.5mmX1.5mm die size.
Baker/Saxena
Simulation and Performance Comparison
DC behavior Transient response
82dB gain
t
s
=275ns
>2.5X figure of merit (FoM).
Baker/Saxena
Flowchart for Three-Stage FD Op-amp Design
Start with the initial
specifications on fun, CL,
Av, and SR.
Does the design meet
specifications?
End
Yes
Design a singly-ended pole-zero cancelled
three-stage op-amp for the given
specifications.
Add a CMFB circuit in the output buffer.
Convert the singly-ended op-amp into a fully
differential one by mirroring it. Use a pair of
diff-pairs for the second stage for robust
biasing.
Simulate the design.
No
Update the value of gm3 corresponding to the
output buffer and recalculate R1C and R2C.
Baker/Saxena
Conclusions
Indirect compensation leads to significantly faster, lower power op-amps
with smaller layout area.
Indirect compensation using split-length devices facilitates low-VDD op-
amp design.
Novel pole-zero canceled three-stage RNIC op-amps exhibit substantial
improvement over the state-of-the-art.
A theory for multi-stage op-amps is presented.
New methodologies for designing multi-stage FD op-amps proposed which
improve the state-of-the-art.
All proposed op-amps are low voltage
Open new avenues for low-VDD mixed signal system design.
Baker/Saxena
Future Scope
Mathematical optimization of PZC op-amps.
Design of low-VDD systems in nano-CMOS process
Pipelined and Delta-Sigma data converters,
Analog filters,
Audio drivers, etc.
Further investigation into indirect-compensated op-amps for n4 stages.
Baker/Saxena
References
[1] Baker, R.J., CMOS: Circuit Design, Layout, and Simulation, 2nd Ed., Wiley Interscience, 2005.
[2] Saxena, V., Indirect Compensation Techniques for Multi-Stage Operational Amplifiers, M.S. Thesis, ECE Dept., Boise
State University, Oct 2007.
[3] The International Technology Roadmap for Semiconductors (ITRS), 2006 [Online]. Available:
http://www.itrs.net/Links/2006Update/2006UpdateFinal.htm
[4] Zhao, W., Cao, Yu, "New Generation of Predictive Technology Model for sub-45nm Design Exploration" [Online].
Available: http://www.eas.asu.edu/~ptm/
[5] Slide courtesy: bwrc.eecs.berkeley.edu/People/Faculty/jan/presentations/ASPDACJanuary05.pdf
[6] Leung, K.N., Mok, P.K.T., "Analysis of Multistage Amplifier-Frequency Compensation," IEEE Transactions on Circuits
and Systems I, Fundamental Theory and Applications, vol. 48, no. 9, Sep 2001.
[7] You, F., Embabi, S.H.K., Sanchez-Sinencio, E., "Multistage Amplifier Topologies with Nested Gm-C Compensation,"
IEEE Journal of Solid State Circuits, vol.32, no.12, Dec 1997.
[8] Grasso, A.D., Marano, D., Palumbo, G., Pennisi, S., "Improved Reversed Nested Miller Frequency Compensation
Technique with Voltage Buffer and Resistor," IEEE Transactions on Circuits and Systems-II, Express Briefs, vol.54, no.5,
May 2007.
[9] Lee, H., Mok, P.K.T., "Advances in Active-Feedback Frequency Compensation With Power Optimization and Transient
Improvement," IEEE Transactions on Circuits and Systems I, Fundamental Theory and Applications, vol.51, no.9, Sep
2004.
[10] Eschauzier, R.G.H., Huijsing, J.H., "A 100-MHz 100-dB operational amplifier with multipath Nested Miller
compensation," IEEE Journal of Solid State Circuits, vol. 27, no. 12, pp. 1709-1716, Dec. 1992.
[11] Leung, K. N., Mok, P. K. T., "Nested Miller compensation in low-power CMOS design," IEEE Transaction on Circuits and
Systems II, Analog and Digital Signal Processing, vol. 48, no. 4, pp. 388-394, Apr. 2001.
[12] Leung, K. N., Mok, P. K. T., Ki, W. H., Sin, J. K. O., "Three-stage large capacitive load amplifier with damping factor
control frequency compensation," IEEE Journal of Solid State Circuits, vol. 35, no. 2, pp. 221-230, Feb. 2000.
Baker/Saxena
References contd.
[13] Peng, X., Sansen, W., "AC boosting compensation scheme for low-power multistage amplifiers," IEEE Journal of Solid
State Circuits, vol. 39, no. 11, pp. 2074-2077, Nov. 2004.
[14] Peng, X., Sansen, W., "Transconductances with capacitances feedback compensation for multistage amplifiers," IEEE
Journal of Solid State Circuits, vol. 40, no. 7, pp. 1515-1520, July 2005.
[15] Ho, K.-P.,Chan, C.-F., Choy, C.-S., Pun, K.-P., "Reverse nested Miller Compensation with voltage buffer and nulling
resistor," IEEE Journal of Solid State Circuits, vol. 38, no. 7, pp. 1735-1738, Oct 2003.
[16] Fan, X., Mishra, C., Sanchez-Sinencio, "Single Miller capacitor frequency compensation technique for low-power
multistage amplifiers," IEEE Journal of Solid State Circuits, vol. 40, no. 3, pp. 584-592, March 2005.
[17] Grasso, A.D., Palumbo, G., Pennisi, S., "Advances in Reversed Nested Miller Compensation," IEEE Transactions on
Circuits and Systems-I, Regular Papers, vol.54, no.7, July 2007.
[18] Shen, Meng-Hung et al., "A 1.2V Fully Differential Amplifier with Buffered Reverse Nested Miller and Feedforward
Compensation," IEEE Asian Solid-State Circuits Conference, 2006, p 171-174.