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Principles of VLSI Design CMPE 413

CMOS Basics
MOS: Metal Oxide Semiconductor
Transistors are built on a Silicon (semiconductor) substrate.
Pure silicon has no free carriers and conducts poorly.
Dopants are added to increase conductivity: extra electrons (n-type) or extra holes (p-type)
MOS structure created by superimposing several layers of conducting, insulating and tran-
sistor-forming materials.
Metal gate has been replaced by polysilicon or poly in modern technologies.
There are two types of MOS transistors:
nMOS : Negatively doped silicon, rich in electrons.
pMOS : Positively doped silicon, rich in holes.
CMOS: Both type of transistors are used to construct any gate.
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Principles of VLSI Design CMPE 413
CMOS Basics
nMOS and pMOS
Four terminal devices: Source, Gate, Drain, body (substrate, bulk).
n+
p
Gate Source Drain
bulk Si
SiO
2
Polysilicon
n+
Source
Gate
Drain
n+
n+
p substrate
Thin
Oxide
nMOS
L
W
pMOS
SiO
2
n
Gate Source Drain
bulk Si
Polysilicon
p+ p+
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Principles of VLSI Design CMPE 413
CMOS Basics
CMOS Inverter Cross-Section
n+
n+ p+
glass(insulator)
metal2
metal1
m1-m2 contact (via)
p-substrate contact (cc)
V
DD
n-diffusion contact (cc)
polysilicon gate (poly ) n-transistor
p-transistor
GND
n-substrate contact (cc)
p-diffusion contact (cc)
(source)
(source)
(Out)
layer #1
layer #2
layer #3
n+ p+
p+
n-well (nwell)
(drains)
Cadence Layer's for AMI 0.6mm technology
p substrate (black background)
(nactive)
(pactive)
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Principles of VLSI Design CMPE 413
CMOS Basics
CMOS Cadence Layout
Cadence Layout for the inverter on previous slide
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Principles of VLSI Design CMPE 413
CMOS Basics
MOS Transistor Switches
We can treat MOS transistors as simple on-off switches with a source (S), gate (G) (con-
trols the state of the switch) and drain (D).
1 represents high voltage, V
DD
(5V, 3.3V, 1.8V, 1.2V, <=1.0V today, .....)
0 represent low voltage - GND or V
SS
. (0V for digital circuits)
g
s
d
g = 0
s
d
g = 1
s
d
g
s
d
s
d
s
d
nMOS
pMOS
OFF
ON
ON
OFF
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Principles of VLSI Design CMPE 413
CMOS Basics
Signal Strengths
Signals such as 1 and 0 have strengths, measures ability to sink or source current
V
DD
and GND Rails are the strongest 1 and 0
Under the switch abstraction, G has complete control and S and D have no effect.
In reality, the gate can turn the switch on only if a potential difference of at least V
t

exists between the G and S.
We will look at V
t
in detail later on in the course.
Thus signal strengths are related to Vt and therefore p and n transistors produce signals with
different strengths
Strong 1: V
DD
, Strong 0: GND, Weak 1 :(~V
DD
-V
t
) and Weak 0 :(~GND + V
t
).
0
1
1
1
*** Strong 0*** Weak 1
0
0
Weak 0 *** Strong 1***
0
1
nMOS pMOS
S D
S D
G G
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Principles of VLSI Design CMPE 413
CMOS Basics
CMOS Inverter
THE CONFIGURATION BELOW FOR A BUFFER IS NOT A GOOD IDEA. WHY?
Vdd
CMOS Inverter
P1
N1
A Out
A
O
0
1
1
0
A O
Vdd
N1
A
Out
BAD IDEA
P1
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Principles of VLSI Design CMPE 413
CMOS Basics
NAND and NOR CMOS Gates
A
B
C
A B C
0 0 1
0 1 1
1 0 1
1 1
0
A
B
C
A B C
0 0 1
0 1 0
1 0 0
1 1
0
Vdd
B
Out
A
P1
P2
N1 N2
Vdd
A B
Out
P1 P2
N2
N1
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Principles of VLSI Design CMPE 413
CMOS Basics
Pass Transistor
The off-state of a transistor creates a high impedance condition Z at the drain.
No current flows from source to drain. So transistors can be used as switches.
However, as we previously discussed this will produce degraded outputs, if only one
transistor is used as a switch.
g
s d
g = 0
s d
g = 1
s d
0 strong 0
Input Output
1 degraded 1
g
s d
g = 0
s d
g = 1
s d
0 degraded 0
Input Output
strong 1
g = 1
g = 1
g = 0
g = 0
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Principles of VLSI Design CMPE 413
CMOS Basics
Transmission Gates
P1
N1
In
Out
A
A
One pMOS and one nMOS in parallel.
Note that neither transistor is connected to V
DD
or GND.
A and A control the transmission of a signal on In to Out.
Transmission gates act as tristate buffers.
g = 0, gb = 1
a b
g = 1, gb = 0
a b
0 strong 0
Input
Output
1
strong 1
g
gb
a
b
a b
g
gb
a b
g
gb
a b
g
gb
g = 1, gb = 0
g = 1, gb = 0
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Principles of VLSI Design CMPE 413
CMOS Basics
Transmission Gate Application: Select Mux
How many transistors are required to implement this using CMOS gates?
Select
In Out
Select
V
DD
Select
Select
Out
A
B
Transmission Gate 2-to-1 MUX
Select Out
0
1
B
A
Truth Table for 2-to-1 MUX
Out =A.S +B.S
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Principles of VLSI Design CMPE 413
CMOS Basics
D Latch
CLK
D Q
L
a
t
c
h
D
CLK
Q
Positive
level-sensitive
latch
1
0
D
CLK
Q
CLK
CLK
CLK
CLK
D Q
Q
Q
If CLK is unavailable one extra inverter
needed to generate it using CLK
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Principles of VLSI Design CMPE 413
CMOS Basics
D Flip-Flop
Positive
edge-triggered
flip-flop
F
l
o
p
CLK
D Q
D
CLK
Q
master-slave
flip-flop
a.k.a
QM
CLK
CLK
CLK
CLK
Q
CLK
CLK
CLK
CLK
D
L
a
t
c
h
L
a
t
c
h
D Q
QM
CLK
CLK
If CLK is unavailable one extra inverter needed to generate it using CLK
Master
Slave
Master Slave
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Principles of VLSI Design CMPE 413
CMOS Basics
D Flip-Flop Operation
CLK =1
D
CLK =0
Q
D
QM
QM
Q
D
CLK
Q
QM follows D, Q is latched
QM transferred to Q, QM latched
Positive
edge-triggered
flip-flop
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Principles of VLSI Design CMPE 413
CMOS Basics
More CMOS Gates
Vdd
Vdd
Out
P1
P2
N2
N1
B
A
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Principles of VLSI Design CMPE 413
CMOS Basics
And More CMOS Gates
B
A
B
Out
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Principles of VLSI Design CMPE 413
CMOS Basics
And More CMOS Gates
Vdd
A
B
C
D
N2
N3 N4
N1
P1 P2
P4
P3
OAI