Instruction Set Architecture

(ISA)
so,ware
instruc(on set

hardware

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Complex vs. Simple Instruc(ons

Complex instruc(on: An instruc(on does a lot of work, e.g. many
opera(ons
Insert in a doubly linked list
Compute FFT
String copy
Simple instruc(on: An instruc(on does small amount of work, it
is a primi(ve using which complex opera(ons can be built
Add
XOR
Mul(ply

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Complex vs. Simple Instruc(ons

Advantages of Complex instruc(ons
+ Denser encoding smaller code size beMer memory
u(liza(on, saves o-chip bandwidth,
(beMer packing of instruc(ons)
+ Simpler compiler: no need to op(mize small instruc(ons as
much

Disadvantages of Complex Instruc(ons
- Larger chunks of work compiler has less opportunity to
op(mize (limited in ne-grained op(miza(ons it can do)
- More complex hardware transla(on from a high level to
control signals and op(miza(on needs to be done by hardware

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ISA-level Tradeos: Seman(c Gap

Where to place the ISA? Seman(c gap
Closer to high-level language (HLL) Small seman(c gap,
complex instruc(ons
Closer to hardware control signals? Large seman(c gap,
simple instruc(ons
RISC vs. CISC machines
RISC: Reduced instruc(on set computer
CISC: Complex instruc(on set computer
FFT, QUICKSORT, POLY, FP instruc(ons
VAX INDEX instruc(on (array access with bounds checking)

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ISA-level Tradeos: Seman(c Gap

Simple compiler, complex hardware vs.
complex compiler, simple hardware
Transla(on (indirec(on) can change the tradeo!
Burden of backward compa(bility
Performance?
Op(miza(on opportunity:
Instruc(on size, code size

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Memory Address
Interpre(ng memory address
Big Endian
LiMle Endian

Instruc(on misalignment
Addressing mode

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Kinds of Addressing Modes

OP
Addressing Mode
Register direct
Immediate (literal)
Direct (absolute)
Register indirect
Base+Displacement
Base+Index
Scaled Index
Autoincrement
Autodecrement
Memory Indirect

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Ri Rj

memory

value in [ ] is the operand

[Ri]
v
M[v]
M[[Ri]]

M[[Ri] + v]
M[[Ri] + [Rj]]
M[[Ri] + [Rj]*d + v], e.g. d=8
reg. file
M[[Ri]+1]
M[[Ri] - 1]
R
M[ M[Ri] ]

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VAX-11
Variable format, 2- and 3-address instruc(ons
Byte 0
OpCode

A/M

A/M

m
A/M

32-bit word size, 16 GPR (4 reserved)

Rich set of addressing modes (apply to any operand)
Rich set of opera(ons
bit eld, stack, call, case, loop, string, poly, system
Rich set of data types
Condi(on codes

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ISA-level Tradeos: Instruc(on Length

Fixed length: Length of all instruc(ons the same

+ Easier to decode single instruc(on in hardware

+ Easier to decode mul(ple instruc(ons concurrently
-- Wasted bits in instruc(ons
-- Harder-to-extend ISA (how to add new instruc(ons?)

Variable length: Length of instruc(ons dierent (determined by

opcode and sub-opcode)
+ Compact encoding
Intel 432: Human encoding (sort of). 6 to 321 bit instruc(ons.
-- More logic to decode a single instruc(on
-- Harder to decode mul(ple instruc(ons concurrently

Tradeos

Code size (memory space, bandwidth, latency) vs. hardware complexity

ISA extensibility and expressiveness
Performance? Smaller code vs. complex decode
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ISA-level Tradeos: Uniform Decode

Uniform decode: Same bits in each instruc(on correspond to the same
meaning
Opcode is always in the same loca(on
DiMo operand speciers, immediate values,
Many RISC ISAs: Alpha, MIPS, SPARC
+ Easier decode, simpler hardware
+ Enables parallelism: generate target address before knowing the
instruc(on is a branch
-- Restricts instruc(on format (fewer instruc(ons?) or wastes space
Non-uniform decode
e.g., opcode can be the 1st-7th byte in x86
+ More compact and powerful instruc(on format
-- More complex decode logic
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x86 vs. Alpha Instruction Formats

x86:

Alpha:
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MIPS Instruc(on Format

R-type, 3 register operands
0

6-bit

rs

5-bit

rt

5-bit

rd

5-bit

R-type

shamt funct
5-bit

6-bit

I-type, 2 register operands and 16-bit immediate operand

opcode rs
6-bit

5-bit

rt

5-bit

I-type

immediate
16-bit

J-type, 26-bit immediate operand

opcode immediate
J-type
6-bit
26-bit
Simple Decoding
4 bytes per instruc(on, regardless of format
must be 4-byte aligned (2 lsb of PC must be 2b00)
format and elds easy to extract in hardware
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A Note on Length and Uniformity

Uniform decode usually goes with xed length
In a variable length ISA, uniform decode can be
a property of instruc(ons of the same length
It is hard to think of it as a property of instruc(ons
of dierent lengths

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ISA Classification
# Memory Max. no. of
Type of Examples
Address operands architecture
allowed
0
3
Load-Store Alpha, ARM,
MIPS,
PowerPC
1
2
Reg-Mem IBM360, Intel
x86, 68000
2
2
Mem-Mem VAX
3
3
Mem-Mem VAX
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ISA Classification
Type

Adv

Disadv

Reg-Reg Simple, xed length encoding, Higher instruc(on count,

simple code genera(on, all
lower instruc(on density
instr. Take same no. of cycles
Reg-
Mem

Data can be accessed without

separate load instruc(on rst,
instruc(on format tend to be
easy to encode and yield good
density

Encoding register no and

memory address in each
instruc(on may restrict the
no. of registers.

Mem-
Mem

Most compact, doesnt waste

registers for temporaries

Large varia(on in
instruc(on size, large
varia(on in in amount of
work (NOT USED TODAY)

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Thank You
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