19ECE384 OPEN LAB

Evaluation I

Soft-Error-Aware SRAM With Multinode Upset

Tolerance for Aerospace Applications
Batch ID:TID 28

Team members: Mentor

BL.EN.U4ECE21075 - L S Krishna Ms. Sonali Agrawal
Maanas Asst. Prof. (Sr. Gr.)
BL.EN.U4ECE21071 - Krishna R Department of ECE
Marar
BL.EN.U4ECE21028 - Charugundla
Bhavitha
Motivation
Problem statement
• Numerous electronic devices operate in complex radiation environments, such as specific mines, space, etc.
Designing an SRAM that can function in these complex operating environments is a challenging task.
• As technology scales down, the critical charge of vulnerable nodes decreases, making SRAM cells more
susceptible to soft errors in the aerospace industry.
• SRAM cells have lower node capacitance and a larger sensitive volume per bit, making them more vulnerable to
the influence of Single Event Upset (SEU).
Why it is important to solve this Problem
• Soft errors can lead to invalid data changes stored in SRAM memories, impacting the reliability and integrity of the
stored information.
• Soft-Error-Aware 16T (S8P8N) SRAM cell addresses the issue of soft errors.
• S8P8N cell can self-recover from the effects of transient pulses of any intensity and polarity at any single sensitive
node. Additionally, S8P8N performs well when subjected to Single Event Multinode Upset (SEMNU).
Applications
• S8P8N is a promising SRAM cell that offers superior radiation resistance and is well-suited for use in aerospace
applications, offering a balanced overhead.
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Objectives

Design and implementation of Low-power, High-speed Soft-Error-Aware SRAM with Multinode Upset Tolerance.

Sub-objectives

1) To review relevant literatures to understand the soft error aware SRAM.

2) To learn Cadence Virtuoso tool to design SRAM models with 45nm technology.

3) To design and implement SRAM with 8-PMOS and 8-NMOS (S8P8N) [1].

4) To design and implement Soft-Error-Aware 14 Transistors (SEA-14T) [2] .

5) To analyze and compare the performance of S8P8N [1] with SEA-14T [2] concerning the parameters, Read
Access Time (RAT), Write Access Time (WAT), power, delay, and stability.

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Literature Survey
BASE PAPER [1]: Soft-Error-Aware SRAM With Multinode Upset Tolerance for Aerospace Applications

N. Bai, X. Xiao, Y. Xu, Y. Wang, L. Wang, and X. Zhou, "Soft-Error-Aware SRAM With Multinode Upset Tolerance for Aerospace Applications,"
in IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, vol. 32, no. 1, pp. 128-136, Jan. 2024.

OBJECTIVE:

• Soft-Error-Aware 16T (S8P8N) SRAM cell for aerospace applications to address the issue of soft errors.

METHODOLOGY:

• The approach involves decreasing the impact of soft errors by altering the topology design of the circuit.

• This reinforcement method is simple and effective, though it often requires an increase in area and power
consumption to achieve better device performance.

INFERENCE:

• In critical environments, S8P8N has a good performance, it offers a reduction in the write delay and read delay.

• S8P8N has the highest New Electrical Quality Metric (NEQM). 4

Literature Survey

SCHEMATIC:

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Literature Survey
PAPER [2]: Design of Soft-Error-Aware SRAM With Multi-Node Upset Recovery for Aerospace Applications

S. Pal, S. Mohapatra, W. -H. Ki and A. Islam, "Design of Soft-Error-Aware SRAM With Multi-Node Upset Recovery for Aerospace
Applications," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 6, pp. 2470-2480, June 2021.

OBJECTIVE:

• Soft-Error-Aware 14T (SEA14T) SRAM cell for aerospace applications to address the issue of soft errors.

METHODOLOGY:

• The traditional SRAM cell is modified such that it can retain its state, even if the stored data are flipped by a
Single Event Upset (SEU) or Single Event Multinode Upset (SEMNU).

INFERENCE:

• Cell is capable of fully recovering from SEUs, induced at any sensitive node, of any strength and polarity.
Moreover, SEA14T is also capable of fully recovering from SEMNUs induced at the internal node-pair.

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Literature Survey

SCHEMATIC & TABLE :

WL Mode of (BL, BLB) Status of Transistors Read/ Write

Operation
1 Write Mode (0, 1) ‘ON’- P2, P3, ‘OFF’- P1, P4, Write
P6, N1, N4, N5, P5, N2, N3, N6
N7, N8
0 Hold Mode (1, 1) ‘ON’- P1, P4, ‘OFF’- P2, P3, nil
P6, N2, N3, N5 P5, N1, N4, N6,
N7, N8
1 Read Mode (1, 1) ‘ON’- P6, N1, ‘OFF’- P1, P2, Read
N2, N3, N4, N5, P3, P4, P5, N6
N7, N8
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Literature Survey
PAPER [3]: Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability From Single-
Node and Double-Node Upsets

A. Yan et al., "Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability From Single-Node and Double-Node Upsets,"
in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 12, pp. 4684-4695, Dec. 2020.

OBJECTIVE:

• Radiation-hardened SRAM cell design S4P8N, with enhanced self-recoverability from Single-node upsets (SNUs) and
Double-node upsets (DNUs).

METHODOLOGY:

• An access-operation optimized SRAM cell whose storage part includes 8 PMOS and 4 NMOS transistors. The access
operations of the proposed cells are optimized using four parallel access transistors.

INFERENCE:

The proposed S4P8N and S8P4N cells can be effectively applied to fields such as low-orbit aerospace and terrestrial
safety-critical applications, where the DNU issue is not severe. 8
Literature Survey
PAPER [4]: Energy-Efficient Dual-Node-Upset-Recoverable 12T SRAM for Low-Power Aerospace Applications

S. Pal, G. Chowdary, W. -H. Ki and C. -Y. Tsui, "Energy-Efficient Dual-Node-Upset-Recoverable 12T SRAM for Low-Power Aerospace
Applications," in IEEE Access, vol. 11, pp. 20184-20195, 2023 .

OBJECTIVE:

• An energy-efficient dual-node-upset recoverable 12T SRAM cell EDP12T, for low-power aerospace applications.

METHODOLOGY:

• The layout of EDP12T is designed such that the required distance between the nodes are maintained to avoid a
multi-node upset at the specific {Q-S1 (Q-S0) } node-pair.

INFERENCE:

• SRAM cell, EDP12T, is fully tolerant to SEUs occurring at all its sensitive nodes.

• In addition, EDP12T fully recovers from SEMNUs that have occurred at its internal node-pair. For aerospace
applications, EDP12T is thus a better choice.
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Literature Survey
PAPER [5]: A Design of Low Power Full Seu Tolerance RHBD 10t Sram Cell

S. K. K, K. P. B, V. M and R. K. R. D V, "A Design of Low Power Full Seu Tolerance RHBD 10t Sram Cell," 2020 IEEE India Council
International Subsections Conference (INDISCON), Visakhapatnam, India, 2020.

OBJECTIVE:

• To design a RHBD 10T SRAM cell for improving power efficiency in the aerospace radiation environment
while preserving the benefits of maximum SEU tolerance, small area, and high stability.

METHODOLOGY:

• The methodology involves simulating the proposed RHBD 10T SRAM cell using Cadence software with a
virtuoso tool from 45-nm CMOS nanotechnology.

INFERENCE:

• RHBD 10 T SRAM can be considered as the best option for terrestrial and aerospace applications, and it
offers the best parameters such as power, delay, and reliability for SEU mechanism.
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 Summary of Literature Survey
Title Problem Methodology/Tools used Final Outcomes Gaps identified
Addressed
Soft-Error-Aware Soft-Error-Aware 16T In critical environments, S8P8N has S8P8N exhibits area
Altering the topology design of the circuit is
SRAM With (S8P8N) SRAM cell a good performance, it offers a penalties. .
Multinode Upset for aerospace simple and effective, though it often requires reduction in the write delay and read
Tolerance for applications to address delay.S8P8N has the highest NEQM.
an increase in area and power consumption to
Aerospace the issue of soft errors.
Applications achieve better device performance.
SMIC (65-nm CMOS technology)

Design of Soft- Soft-Error-Aware 14T A slightly larger area

The traditional SRAM cell is modified such Cell is capable of fully recovering
Error-Aware SRAM (SEA14T) SRAM cell overhead.
With Multi-Node for aerospace that it can retain its state, even if the stored from SEUs, induced at sensitive
Upset Recovery for applications to address
data are flipped by an SEU or SEMNU. node. Moreover, it is also capable of
Aerospace the issue of soft errors.
Applications (65-nm CMOS technology.) fully recovering from SEMNUs
induced at the internal node-pair.

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Summary of Literature Survey
Title Problem Addressed Methodology/Tools used Final Outcomes Gaps identified

Novel Speed-and- The access operations of the It can recover only from a
Radiation-hardened SRAM The SRAM cell can be
Power-Optimized proposed cells are optimized using part of DNUs. It has small
SRAM Cell Designs cell design with enhanced four parallel access transistors. effectively applied to fields overhead in terms of power
With Enhanced Self- Tools Used: Synopsys HSPICE tool. dissipation.
self-recoverability from such as low-orbit aerospace
Recoverability From
Single- and Double- single-node upsets (SNUs) and terrestrial safety-critical
Node Upsets
and Double-node upsets applications, where the DNU
(DNUs). issue is not severe.
Energy-Efficient An energy-efficient dual- EDP12T, is fully tolerant to A slight penalty in the read
The layout is designed to avoid a
Dual-Node-Upset- node-upset recoverable 12T SEUs occurring at all its delay.
Recoverable 12T SRAM cell EDP12T, for low- multi-node upset at the specific {Q- sensitive nodes.
SRAM for Low- power aerospace applications.
S1 (Q-S0) } node-pair.
Power Aerospace
Applications (65-nm CMOS technology.)

A DESIGN OF LOW To design a SRAM cell for
POWER FULL SEU improving power efficiency
TOLERANCE RHBD in the aerospace radiation
10T SRAM CELL environment while preserving
the benefits of maximum SEU
tolerance, small area, and
high stability.
The methodology involves
simulating the proposed RHBD 10T
SRAM cell.
Tools Used: Cadence Virtuoso
(45-nm CMOS technology).
RHBD 10 T SRAM cell in this
paper can store a single bit. It
is the best option for terrestrial
and aerospace applications and
offers the best parameters such
as power, delay, and reliability
for SEU mechanism.
This SRAM cell tolerates
only single event upsets of 0
to 1 and 1 to 0.It can store
only a single bit.
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Conceptual Architecture

(WL, Mode of (BL, BLN) Status of Transistors Read/

WWL) Operation Write

(1, 0) Write (0, 1) ‘ON’- P3, P4, ‘OFF’- P1, P2, Write ‘0’
Mode P5, P7, P8, N2, P6, N1, N5, N6
N3, N4, N7, N8
(1, 0) ‘ON’- P1, P2, ‘OFF’- P3, P4, Write ‘1’
P6, P7, P8, N1, P5, N2, N3, N4
N5, N6, N7, N8
(0, 1) Hold Mode (1, 1) ‘ON’- P1, P2, ‘OFF’- P3, P4, nil
P6, N1, N5, N6 P5, P7, P8, N2,
N3, N4, N7, N8
(1, 1) Read Mode (0, 1) ‘ON’- P5, N4, ‘OFF’- P6, P7, Read ‘0’
N7, N8 P8, N4
(1, 0) ‘ON’- P6, N5, ‘OFF’- P5, P7, Read ‘1’
N7, N8 P8, N4

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 Specifications

• The specific design of the S8P8N cell, which includes two storage nodes (Q and QN) and two internal nodes (S0 and S1).
• The internal node S0 is connected to the bit line (BL) and S1 is connected to bit line (BLN) .
• The storage nodes Q and QN is connected to bit lines BL and BLN, respectively.
• Assuming Q, QN, S0, S1 store values of “1” , “0”, “1” and “0” respectively.
• When the drain of an N-MOS is struck by a radiation particle, it produces a transient pulse of either “1” → “0” or “0” →
“0”.
• Conversely, for a P-MOS, it produces either a “1”→ “1” or “0” → “1” transient pulse.
• So the stored value of Q and S1 remains unchanged as they are connected to PMOSs and NMOSs drain respectively.
• Thus, the sensitive nodes are QN and S0 when the proposed S8P8N cell’s store value is “1”. 14
Specifications

SEU Tolerance
1) SEU at QN:
• When the initial storage value of node QN is “0” and an SEU changes it to “1”.
• Q and S1 maintain their original states.
• The node QN can self-recover depending on the working of N2, N3, P1, P2, P3, P5, N5, P6, N6 and P4 transistors.
2) SEU at S0:
• When the initial storage value of node S0 is “1” and an SEU changes it to “0”.
• The states of Q and S1 remain unchanged.
• The node S0 can self-recover depending on the working of P5, N5, N2, N3, P1, P2, N1 and N4 transistors.
3) SEU at QN-S0:
• The appearance of an SEMNU changes the values of nodes QN and S0 to “1” and “0,” respectively.
• Depending on the working of P5, N3, P1, P5, N3, N5, P3 and N2 transistors, eventually, the stored data change through a feedback
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loop.The proposed cell can recover its initial state completely in case of a soft error occurring at node QN and S0.
Design and Implementation

Sub-objective 1 :
To design and implement SRAM with 8-PMOS and 8-NMOS (S8P8N) [1].

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Design and Implementation
Schematic of S8P8N
Design Specifications

Tool Used Cadence Virtuoso

Technology 45nm

Transistor Width (W) 120nm

265nm(N4,N5)

Transistor Length (L) 45nm

VDD 0.8 V

Vpulse 1.2 V

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Design and Implementation
Simulation Results of S8P8N
Write ‘0’

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Design and Implementation
Simulation Results of S8P8N
Write ‘1’

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Design and Implementation
Simulation Results of S8P8N
Hold Mode

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Design and Implementation
Simulation Results of S8P8N
Read ‘0’

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Design and Implementation
Simulation Results of S8P8N
Read ‘1’

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Applications/Social Relevance

The main goal of this technology is to improve the reliability and robustness of electronic systems used in
aerospace applications, such as.
1) Spacecraft Onboard Computing
• Spacecraft operate in harsh radiation environments where cosmic rays and solar radiation can cause soft errors in
electronic components.
2) Satellite Systems
• Satellites are exposed to radiation in the space environment, which can cause bit flips and other errors in their memory
systems
3) Avionics Systems
• Aircraft, especially those operating at high altitudes or in polar regions, are also subject to increased radiation
exposure which can cause soft errors.
4) Unmanned Aerial Vehicles (UAVs)
• These vehicles often operate in remote or hostile environments where radiation exposure may pose a threat to onboard
electronics.

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Work Done
• Basics of SRAM
• Learnt Cadence Virtuoso tool.
• Designed and simulated S8P8N for three different modes (Read ,Write & Hold).

Work To Be Done
• To design and simulate SEA-14T for three different modes.
• Comparison of parameters between SEA 14T and S8P8N

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References
[1] N. Bai, X. Xiao, Y. Xu, Y. Wang, L. Wang and X. Zhou, "Soft-Error-Aware SRAM With Multinode Upset
Tolerance for Aerospace Applications," in IEEE Transactions on Very Large-Scale Integration (VLSI) Systems,
vol. 32, no. 1, pp. 128-136, Jan. 2024, doi: 10.1109/TVLSI.2023.3328717.
[2] S. Pal, S. Mohapatra, W. -H. Ki and A. Islam, "Design of Soft-Error-Aware SRAM With Multi-Node Upset
Recovery for Aerospace Applications," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68,
no. 6, pp. 2470-2480, June 2021, doi: 10.1109/TCSI.2021.3064870.
[3] A. Yan et al., "Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability
From Single- and Double-Node Upsets," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol.
67, no. 12, pp. 4684-4695, Dec. 2020, doi: 10.1109/TCSI.2020.3018328.
[4] S. Pal, G. Chowdary, W. -H. Ki and C. -Y. Tsui, "Energy-Efficient Dual-Node-Upset-Recoverable 12T
SRAM for Low-Power Aerospace Applications," in IEEE Access, vol. 11, pp. 20184-20195, 2023, doi:
10.1109/ACCESS.2022.3161147.`
[5] S. K. K, K. P. B, V. M and R. K. R. D V, "A Design of Low Power Full Seu Tolerance RHBD 10t Sram
Cell," 2020 IEEE India Council International Subsections Conference (INDISCON), Visakhapatnam, India,
2020, pp. 27-32, doi: 10.1109/INDISCON50162.2020.00018.

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[6] S. Pal, G. Chowdary, W.-H. Ki, and C.-Y. Tsui, “Energy-efficient dual-node-upset-recoverable 12T SRAM
for low-power aerospace applications,” IEEE Access, vol. 11, pp. 20184–20195, 2023, doi:
10.1109/ACCESS.2022.3161147.
[7] C. Peng et al., “Radiation-hardened 14T SRAM bitcell with speed and power optimized for space
application,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 27, no. 2, pp. 407–415, Feb. 2019, doi:
10.1109/TVLSI.2018.2879341
[8] J. Guo, L. Xiao, and Z. Mao, “Novel low-power and highly reliable radiation hardened memory cell for 65
nm CMOS technology,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 7, pp. 1994–2001, Jul. 2014, doi:
10.1109/TCSI.2014.2304658.
[9] J. Jiang, Y. Xu, W. Zhu, J. Xiao, and S. Zou, “Quadruple cross-coupled latch-based 10T and 12T SRAM bit-
cell designs for highly reliable terrestrial applications,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 66, no. 3,
pp. 967–977, Mar. 2019, doi: 10.1109/TCSI.2018.2872507.
[10] G. Prasad, B. C. Mandi, and M. Ali, “Low power and write-enhancement RHBD 12T SRAM cell for
aerospace applications,” Anal. Integr. Circuits Signal Process., vol. 107, no. 2, pp. 377–388, May 2021, doi:
10.1007/s10470-020-01786-8.

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