Implementation of a SRAM cell

Digital Electronics Lab Section: J

Group: 5

Ashek-Al-Mahady
Id:18-36811-1
Subbmitted to: Naheed Hossain
Submission date: 30-06-2021

Abstract—In today's world, the electronics sector is dealing found in practically every computer in some form [3]. An
with a severe problem: standby leakage current in most SRAM device is simple in concept, comprising of an array
electronic devices. As CPU speeds increase, so does the of latches, as well as control and decoding logic to
requirement for high-speed cache memory growing. Several determine the address being read or written at any given
low-power strategies are utilized to lower the leakage current
time. A SRAM figure is given below:
of SRAM, which is mostly used for cache memory design. For
most digital circuits, the full CMOS 6T SRAM cell is the best
option. This report implements 6T CMOS SRAM and
simulation results.

Keywords—component, formatting, style, styling, insert (key

words)

I. INTRODUCTION
The most significant technological challenge that today's Fig1: SRAM cell with inverter latch.
electronic industry faces is power consumption, particularly
off-state leakage current. Power becomes a key limiting A SRAM latch is made by looping two inverters together.
element in design performance or integration as chip The intended logic state is maintained on one side of the
densities reach a billion or more transistors. The number of loop, while the opposite logic state is maintained on the
transistors per chip and local clock frequencies for high- other. Because an inverter is the simplest logic device to
performance microprocessors will continue to rise design, it is utilized instead of non-inverting buffers. Both
exponentially in the next 10 years, according to forecasts writing and reading are enabled by the two pass transistors
from the International Technology Roadmap for on either side of the latch. When the transistors are turned
Semiconductors (ITRS). As the speed of microprocessor- on during writing, they force each half of the loop to the
based electronic equipment rises, a vast amount of data must state that is driven on the vertical bit lines. The transistors
be processed at a very high rate, which is challenging to turn on as well during reading, but the bit lines are sensed
achieve. As a result, cache memory design has become a rather being driven. Each inverter and the two pass
critical challenge. SRAM is commonly utilized for cache
transistors in a typical SRAM implementation require six
memory design, with complete CMOS 6T SRAM cells being
the most popular choice. Static (or leakage) power affects all transistors.
types of Complementary Metal Oxide Semiconductor
(CMOS) circuits, but it's especially important for Static
Random Access Memories (SRAMs), because memories are
designed with performance as the primary criterion, and
memories are accessed in small chunks, leaving the vast
majority of memory cells un-accessed for a significant
amount of time [1]. According to the International Technical
Roadmap for Semiconductors (ITRS), the proportion of
transistors dedicated to memory structures in
microprocessor-based systems is currently at 70% and is
expected to rise to 80% in the near future [2]. The
requirement for low power has led to the development of
numerous strategies for reducing leakage in SRAM cells at
various levels of abstraction, architectural, device, and circuit
level in recent years.

II. THEORY AND METHODOLOGY

Static RAM, sometimes known as SRAM, is the most basic Fig2: 6-T SRAM cell
and straightforward sort of volatile memory, and it can be
A SRAM cell might be in one of three states. It can be in V. PRECAUTION
one of three states: standby (the circuit is not in use), Because there is a potential fire threat in the circumstance,
reading (data has been requested), or writing (the circuit is the circuit must be inspected before adding electricity to it.
in use) (updating the contents). For read and write modes,
the SRAM should have "readability" and "write stability,"
respectively. The three states function as follows:

VI. EXPERIMENTAL PROCEDURE

1. Open PSpice Schematics
2. Click on “Get New Part then search for required
components and place them over the board
3. Connect Wire to the circuit and save the file.
4. Give period on time to the input
5. Go to Transient Analysis and set value to print step
and final step
6. Set level marker to see the input and output wave
7. Run the simulation

VII. SIMULATIOS
Fig3: SRAM Operaton PSpice simulation circuits are given below:

III. PRE LAB WORK

Determine the operation of a cross-coupled inverter pair,
where an inverter A is driven by another inverter B, while
the inverter B also is driven by inverter A. Here is a cross-
coupled inverter pair figure:

Fig5: Circuit diagram using inverter 7404

Fig4: Cross-coupled inverter pair

IV. APARATUS

1. PMOS
2. NMOS
3. Inverter (7404)
4. Connecting wires
5. Trainer board Fig6: Circuit diagram using CMOS

VIII. SIMULATED RESULTS

Following circuits simulated results: IX. DISCUSSION
We were able to effectively simulate the supplied circuits
using pspice and obtain the desired output values. However,
because to the present pandemic crisis, we were unable to
carry out a real-world implementation. As a result, we have
no real data to compare to the simulated data. But one thing
is certain: these results should be as similar as feasible,
according to the belief.

REFERENCES

[1] Andrea Calimera et al., ‘Design techniques and architectures for low
leakage SRAMs’, IEEE transactions on circuits and systems, vol. 59,
No. 9, pp. 1992–2007, Sept. 2012.J. Clerk Maxwell, A Treatise on
Electricity and Magnetism, 3rd ed., vol. 2. Oxford: Clarendon, 1892,
pp.68–73.
SRAM [2] ‘International technical roadmap for semiconductors’, 2009 available
online at http:// www.itrs. net/links/ 2009ITRS/home2009.htmK.
Elissa, “Title of paper if known,” unpublished.
[3] Thomas L. Floyd, Digital Fundamentals, 9th Edition, 2006, Prentice
Hall.