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VHDL Project Universal Register
VHDL Project Universal Register
Faculty of Engineering
Electrical department
2nd year - 2014
VHDL Report
VHDL Project
Universal Register
Prepared By:
Mohamed Khaled Aly
Mohamed Said
Mohamed Salah Bassuny
Mahmoud Gaber
Marwan Salem
April, 2014
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VHDL Project
Universal Register
VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.all;
use IEEE.STD_LOGIC_unsigned.all;
entity Universal_register_counter is
Port ( clk : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
control : in STD_LOGIC_VECTOR (2 downto 0);
data_sh_r : in STD_LOGIC;
data_sh_l : in STD_LOGIC;
flag : out STD_LOGIC;
output : out STD_LOGIC_VECTOR(7 downto 0));
end Universal_register_counter;
begin
if(rising_edge(clk)) then
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VHDL Project
Universal Register
case control IS
--shift right
--shift left
when "011" => current_data <= current_data(0) & current_data( 7 downto 1 ); --rotate
right
when "100" => current_data <= current_data (6 downto 0)& current_data(7) ; -- rotate
left
when "101" => current_data <= current_data ;
when "110" => current_data <= current_data+1 ;
--store
-- count up
-- count down
-- control error
end case;
flag<='1';
else
flag<='0';
end if;
end if;
end process;
end Behavioral;
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VHDL Project
Universal Register
Schematics
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VHDL Project
Universal Register
Simulation
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