1.2.

2 THERMAL RUNAWAY

For every 10 degree Centigrade rise in temperature I CO doubles itself. It also

increases IC significantly. This causes power dissipation to increase , because of
increase in ICO. For rise in ICO there occurs cumulative increase in IC. This cause

Thermal Runaway which will destroy the transistor.

The increase in the collector current increases the power dissipation at the
collector junction. This in turn further increases the temperature of the junction
and hence increases the collector current. The process is cumulative. The excess
heat produced at the collector base junction may even burn and destroy the
transistor. This situation is called thermal runaway.

1.2 LOAD LINE

1.3.1 DC LOAD LINE-FIXED BIAS CIRCUIT

Fig. 1.5 Fixed Bias Circuit

In this biasing circuit the values of VCC& RC are fixed and IC & VCE are dependent

on RB,
Applying Kirchoffs voltage law,

VCC = ICRC +VCE

To draw DC load line two conditions to apply,
i) To obtain A Q-point co-ordinates
Substitute VCE=0 in above eqn.
VCC = IC RC
IC = VCC / RC

ii) To obtain B co-ordinates

Substitute IC =0 in above eqn.
VCC = VCE
So A [VCE=0, IC = VCC / RC], B [VCC = VCE, IC =0].
IC
C
A
Q

D
B
Fig. 1.6 DC Load Line

VCE

In order to get faithful amplification, the Q-point should be with in the active
region of the transistor i.e. midpoint of the load line.
Operating point should be stable, if Q-point shifts nearer to either A or B, the
output voltage or current gets clipped, there by output signal is distorted.
1.3.2 Q-POINT SHIFTING FACTORS
Reverse saturation current ICO doubles for every 10 degree increase in

temperature.
Base-emitter voltage VBE decreases by 2.5mV per C.
Transistor current gain or hfe increase with temperature.
In fixed bias circuit, IB is kept constant since IB is approximately equal to VCC/RB.
If Transistor is replaced by another transistor, there may be variations in the
parameters such as gain. But IB is same, due to gain IC will change so that

Q-

point shifted and it is operated in the unsatisfactory region.

1.3.3 AC LOAD LINE

After DC load line was drawn, Q-point is fixed at the center, it is drawn under
zero input signal condition.
AC load line also passes through same Q-point, the effective ac load resistance R ac
is given by,
Rac= RC RL
So slope of the AC load lines will be ( -1 / Rac ).
AC load line is drawn between VCE (max) & IC (max).

 VCE (max) = VCEQ + ICQ Rac locates the Q-point D on the VCE axis.
IC (max) = ICQ + (VCEQ / Rac) locates the Q-point C on the IC axis.
If RC>Rac, the DC load line is less steep than AC load line.