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138
Chapter 7
7.1 Introduction
The majority of PLC manufacturers use the ladder logic diagram
programming language to program their programmable logic controllers (PLCs). Some manufacturers prefer using logic gate circuits or
Boolean expressions to program their PLCs. Therefore, it is beneficial to
know how to convert one type of PLC programming language to the
other.
In this chapter, you will learn how to create logic gate circuits
from ladder logic diagrams and vice versa. You will review the functions associated with the combinational logic gates. These gates are
the NOT, AND, OR, NAND, NOR, XOR, and XNOR gates. You will
learn how to create PLC ladder logic diagrams that emulate the functions of these gates.
Introduction
Combinational and Sequential Logic Gate Circuits
Boolean Expressions, Truth Tables, and Logic Gate Circuits
NOT Gates or Inverters
AND Gates
OR Gates
NAND Gates
NOR Gates
XOR (Exclusive OR) Gates
XNOR (Exclusive NOR) Gates
Simplifying Boolean Expressions
Creating PLC Ladder Logic Diagrams from Logic Gate Circuits
Creating PLC Ladder Logic Diagrams from Boolean Expressions
Creating Logic Gate Circuits from PLC Ladder Logic Diagrams
Combinational
logic gates:
Logic devices in which
the output of the device
is dependent only on
the present inputs to
the device. There is no
dependency on past
inputs. Combinational
logic gates do not require
clock pulses to operate.
Sequential
logic devices:
Logic devices in which
the output of the device
is dependent on the
present and past inputs
to the device. Sequential
logic devices require
clock pulses to operate.
Technical Terms
combinational logic gates
sequential logic devices
Boolean expression
Boolean algebra
true state
logic high
false state
logic low
truth table
gate symbols
NOT gate
AND gate
OR gate
NAND gate
NOR gate
XOR gate
XNOR gate
Karnaugh map
Quine-McCluskey routine
Learning Objectives
After completing this chapter, you will be able to:
Describe combinational and sequential logic gate circuits.
Create PLC ladder logic programs for NOT, AND, OR, NAND, NOR,
XOR, and XNOR logic gates.
Create Boolean expressions and logic gate circuits from truth tables.
Use the Logic Converter instrument in NI Multisim to create logic
tables and Boolean expressions from logic gate circuits.
Convert Boolean expressions to PLC ladder logic diagrams.
Convert PLC ladder logic diagrams to logic gate circuits and Boolean
expressions.
AB
AB+AB+C
B
AB
C
Figure 7-1. A three-input logic gate circuit.
137
Chapter 7
139
140
1 k/5 V
+V
1 k/5 V
Clock pulses
+V
0000
XXXX
J
J
Q
JK flip-flop
K Q
1 k/5 V
+V
1 k/5 V
+V
J
K
K Q JK flip-flop
Truth table:
Table used to map
Boolean expressions.
Truth tables contain
Boolean expression
inputs and outputs.
Gate symbols:
Symbols used to display
logic gate devices.
Boolean expression: Y = AB + AC
Truth Table
A
0
0
0
0
1
1
1
1
Figure 7-2. Sequential logic circuit. These circuits require clock pulses.
Boolean expression:
Names for equations in
Boolean algebra.
Boolean algebra:
Form of mathematics
that uses two conditions
or states: true and false.
True state:
State in digital electronics
that is represented with a
number 1.
False state:
State represented in
digital electronics with a
number zero.
Logic high:
State in digital electronics
that is represented with
5 volts. Also called logic
one.
Logic low:
State in digital electronics
that is represented with
zero volts. Also called
logic zero.
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Y
0
1
0
1
0
0
1
1
A
B
AB
Y
AC
C
Figure 7-4. Logic circuit for Boolean expression in Figure 7-3.
Chapter 7
141
142
The output of a NOT gate is the inverse of the input. The NOT
gate is sometimes called an inverter. The function of a NOT gate is
simulated by the electric circuit displayed in Figure 7-5. When the
switch is closed, the electric bulb is short circuited, and it turns off.
When the switch is open, electric current flows through the lightbulb,
and the lightbulb turns on. Like the NOT gate, the output is on when
the input is off and vice versa. The input is inverted to generate an
output. Figure 7-6 displays the NOT logic gate symbol, its Boolean
expression, and its truth table.
Figure 7-7 displays that there are two different types of PLC ladder logic diagrams that perform the NOT function.
In rung 0000, the XIO (examine if open) device is connected to
the output. Therefore, the XIO device is normally closed and
output zero is ON. When you press pushbutton #1 (I:0/0), the
output zero (pilot light #1) is turned off. (Notice that address
I:0/0 references the port 0 on module 0.)
In rung 0001, pushbutton #2 (I:0/1) is connected to internal
coil bit B3:0/0. (Notice that address I:0/1 references the port 1
on module 0.) In rung 0002, the internal contact bit B3:0/0 is
inverted and connected to output one (pilot light #2). When
normally open input I:0/1 is open, output one (O:0/1) is ON.
Press input 0/1 to close it, then output one will turn OFF.
NOT gate:
Gate that generates a
logic high output when
all inputs are logic low.
Pushbutton #1
I:0
5V
Pushbutton #2
I:0
Control relay
B3:0
0001
1
Control relay
Pilot light #2
B3:0
O:0
0002
0003
End
Switch (SW)
O:0
0000
1 k
+
Pilot light #1
7.6 OR Gates
Figure 7-5. Electric circuit emulating the function of a NOT gate.
Boolean expression: Y = A
A
A
0
1
Y
1
0
Truth table
OR gate:
Gate that generates a
logic high output in all
states except when all
inputs are logic low.
The function of an OR gate is simulated in the electric circuit displayed in Figure 7-11. Notice that the lamp will be ON when one or
both of the switches are closed.
Figure 7-12 displays a two-input OR logic gate symbol, its Boolean expression, and its truth table. The truth table shows a logic high
output for all combinations of inputs except where both A and B are
low. When either input A, B, or both are on, the output is on.
Figure 7-13 displays a ladder logic diagram that performs the
function of a two-input OR gate. When either normally open (NO)
inputs I:0/0, I:0/1, or both are closed, output O:0/0 is energized.
Chapter 7
Switch A
143
144
Switch B
Switch A
0
1
Lamp on = 1
1 k
Switch B
Lamp off = 0
Lamp on = 1
1 k
Lamp off = 0
5V
+
5V
A
Y
B
0
1
0
1
Boolean expression: Y = A + B
Y
0
0
0
1
A
Y
Truth table
Two-input OR gate
A
0
0
1
1
B
0
1
0
1
Y
0
1
1
1
Truth table
OR Logic Gate
Pilot light #1
O:0
0000
0
0001
Pushbutton #1
Pilot light #1
I:0
O:0
0000
Pushbutton #2
I:0
End
End
Chapter 7
145
146
NAND gate:
Gate that does not
generate a logic high
output when all inputs
are logic low. An
inverted AND.
When both normally open inputs I:0/2 and I:0/3 are energized
(closed), the relay coil B3:0/0 is energized. Then the normally
closed contact B3:0/0 is opened to turn off output O:0/1.
The function of a NOR logic gate is simulated in the electric circuit displayed in Figure 7-17. Notice that the lamp will be ON when
both switches are open. The NOR gate takes its name from NOT and
OR. Its outputs are the inverse of the OR gate.
NAND Logic Gate
Pushbutton #1
Pilot light #1
I:0
O:0
0000
Pushbutton #2
I:0
1
Switch A
1
Creating NAND logic gate using AND and NOT logic gates.
Control relay
Pushbutton #3 Pushbutton #4
I:0
I:0
B3:0
Lamp on = 1
1 k
+
5V
Lamp off = 0
1
Switch B
0001
2
Y =AB
Y=AB
O:0
0003
AB
A
0
0
1
1
B
0
1
0
1
End
Boolean expression: Y = A B = A + B
0
Pilot light #2
0002
Control relay
B3:0
Y
1
1
1
0
Switch B
0
Switch A
0
1 k
Lamp off = 0
Truth table
NAND gate
Figure 7-15. Boolean expression, gate symbol, and
truth table for a NAND logic gate.
Lamp on = 1
+
5V
Chapter 7
147
Y=A+B
Y=A+B
A
0
0
1
1
B
0
1
0
1
Y
1
0
0
0
Truth table
A+B
When both normally open inputs I:0/2 and I:0/3 are de-energized,
the relay coil B3:0/0 is de-energized. Then the normally closed
contact B3:0/0 remains closed to turn on output O:0/1.
Boolean expression: Y = A + B = A B
B
148
NOR gate
Switch A
Switch B
I:0
Pushbutton #2
I:0
Pushbutton #1
O:0
Lamp on = 1
0000
1 k
Lamp off = 0
5V
3
Control relay
B3:0
Pushbutton #4
I:0
Boolean expression: Y = A + B = A B + A B
Pilot light #2
O:0
0002
0
XOR gate
0003
End
A
0
0
1
1
B
0
1
0
1
Y
0
1
1
0
Figure 7-21. Boolean expression, gate symbol, and truth table for
an XOR logic gate.
Chapter 7
149
150
Boolean expression: Y = A + B = A B + A B
Pilot light #1
Pushbutton #2
I:0
O:0
0000
0
Pushbutton #1
I:0
Pushbutton #2
I:0
A
B
A
0
0
1
1
B
0
1
0
1
Y
1
0
0
1
XNOR gate
0001
End
Figure 7-25 displays that there are two different types of ladder
logic diagrams that perform the XNOR function.
Both inputs I:0/0 and I:0/1 must be on or off to turn on the
output O:0/0.
When I:0/2 is on and input I:0/3 is off or vice versa (i.e., XOR
gate), the relay coil B3:0/0 is energized. Then the normally
closed contact B3:0/0 opens to turn off output O:0/1.
Switch A
XNOR gate:
Gate that generates a
logic high output when
either both inputs are
logic high or both inputs
are logic low.
Switch B
Lamp on = 1
1 k
Lamp off = 0
Karnaugh Maps
+
5V
Karnaugh map:
A tool that can be used
to simplify Boolean
expressions. This is an
older, difficult method
for Boolean expression
simplification.
Chapter 7
151
152
Pushbutton #2
I:0
Pilot light #1
Pushbutton #1
I:0
Pushbutton #2
I:0
A
0
0
1
1
O:0
0000
1
Pushbutton #2
I:0
Control relay
Pilot light #2
B3:0
O:0
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
B
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
C
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
Notice that the input values are placed so that the values for adjacent
columns and rows change only a single bit. For example, for a threeinput K-Map, binary numbers related to inputs A and B are placed
above the columns in the order 00, 01, 11, and 10. Binary numbers
related to input C are placed to the left of the rows in the order 0 and 1.
This ordering follows the Gray code system explained in Chapter 3.
To use the K-Map, the expression must be in a sum of products
(SOP) form, such as AB + BC. This means that the Boolean expression consists of groups that are created from ANDed inputs. Then, the
groups are summed (ORed) to create the entire Boolean expression.
Use the following steps and refer to Figure 7-27 to simplify the Boolean expressions using K-Maps.
1. Select an appropriate K-Map that has the correct number of
input boxes, such as two-input and three-input. As stated, for
an n-variable input truth table, there will be 2n boxes. Therefore,
for a two-variable (A and B) input table, there will be 22 boxes, or
4 boxes.
End
AB
Y
C
00
01
11
10
01
11
10
0002
0003
A
B
0001
0
Creating XNOR logic gate using XOR and NOT logic gates.
Control relay
Pushbutton #1 Pushbutton #2
I:0
B3:0
I:0
Pushbutton #1
I:0
B
0
1
0
1
A
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
AB
CD
00
00
01
11
10
Chapter 7
153
154
A
0
B
0
A
Correct
Incorrect
AB
0
00
01
11
10
00
01
11
10
C
Group
of 2
Correct
Incorrect
AB
Group
of 3
C
Group
of 4
Group
of 5
B
Correct
A
0
Incorrect
A
1
C
Incorrect
Correct
AB
00
01
11
10
AB
00
01
11
10
D
Incorrect
Correct
AB
C
Leftmost cell
00
Top cell
01
1
11
10
Rightmost cell
E
Bottom cell
Figure 7-27. Simplifying Boolean expressions using K-Maps. AGrouping pairs of binary 1s in
adjacent cells. BGrouping even number of 1s in adjacent cells. CGrouping 1s in the adjacent
cells. DGroups must be as large as possible. EGroups can wrap around the K-Map.
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Y
0
0
1
0
1
0
1
1
AB
C
Group 1
00
01
11
10
1
Group 3
Group 2
Chapter 7
155
156
Example 7-1
Example 7-2
Quine-McCluskey Routine
For more than five inputs, the Karnaugh map method becomes
very difficult. Therefore, for more than five input variables, the
Quine-McCluskey routine is a better method for simplifying Boolean
expressions. The Quine-McCluskey routine is a complicated method
that uses the Boolean algebraic simplification rules to find the simplified Boolean expression. We will not study the theory of the QuineMcCluskey method in this textbook, but you should know that this
method exists and might be used in an advanced course.
Quine-McCluskey
routine:
Tool used as an advanced
Boolean expression
simplification routine.
Truth Table:
Example 7-1
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Y
0
1
0
1
0
1
0
1
AB
C
00
01
11
10
0
Group 1
1
Figure 7-29. Using a Karnaugh map to find a simplified Boolean expression for Example 7-1.
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Y
0
0
0
1
0
1
0
1
0
0
0
1
0
1
1
0
Chapter 7
157
Logic converter
instrument
Select A-D
158
Output column
Example 7-3
Simplify
button
Simplified
Boolean
expression
Figure 7-31. Using the Logic Converter instrument to find the simplified
Boolean expression for Example 7-2.
Example 7-2
ACD + BCD + BCD + ABC D = Y
A
I:0
C
I:0
D
I:0
O:0
ACD
0000
3
B
I:0
I:0
I:0
BCD
B
I:0
I:0
I:0
Create the PLC ladder logic diagram for the logic gate circuit displayed in Figure 7-33.
Examine Figure 7-33. The pilot light red (PLTR) output section
has three inputs: PBR, PBG, and SW. Pushbutton red (PBR) and pushbutton green (PBG) are inputs to an XOR logic gate. The output of
the XOR logic gate and the inverted switch (SW) are inputs to a twoinput AND logic gate. These inputs generate the pilot light red (PLTR)
output.
The two-input AND logic gate output is also fed into a two-input
NAND logic gate. The temperature switch (TSW) is another input to
the NAND logic gate. The output generated from the NAND logic
gate is labeled pilot light white (PLTW).
Using the transformations described in Section 7.7 (on NAND
gates) and Section 7.9 (on XOR gates), you can generate a PLC ladder
logic diagram. Figure 7-34 displays the PLC ladder logic diagram for
Example 7-3.
PBR
PBG
PLTR
SW
BCD
A
I:0
I:0
I:0
I:0
PLTW
TSW
Figure 7-33. Logic gate circuit for Example 7-3.
0001
ABCD
End
Chapter 7
159
160
Example 7-3
PBR
XOR
PBG
AND
NOT
SW
NAND
PBR
PBG
TSW
SW
PLTR
PBR
I:0
SW
I:0
PLTR
TSW
O:0
0000
0
PBR
I:0
PBG
I:0
XOR
NOT
AND
output
Example 7-4
AND
AND
PBR
PLTW
TSW
I:0
NAND
output
PBG
O:0
0001
OR
SW
AND
NOT
3
0002
NAND
PLTR
TSW
End
PBR
I:0
PBG
I:0
TSW
I:0
PLTR
AND
NOT
O:0
0000
0
Example 7-4
Create the PLC ladder logic diagram for the logic gate circuit displayed in Figure 7-35.
Pushbutton red (PBR) and pushbutton green (PBG) are inputs to a
two-input AND gate. The output of the AND logic gate and the switch
(SW) are inputs to a two-input OR logic gate. The output of the OR
logic gate and an inverted temperature switch (TSW) are inputs to a
second AND logic gate. This AND logic gate generates the output for
pilot light red (PLTR).
SW
I:0
2
OR
AND
0001
End
Chapter 7
161
162
Example 7-5
Example 7-5
Create the PLC ladder logic diagram for the logic gate circuit displayed in Figure 7-37.
Inputs A and B are fed into an XNOR logic gate. Inputs D and E
are fed into a NOR logic gate. Outputs of the XNOR and NOR logic
gates plus input C are fed into a three-input OR logic gate. The threeinput OR logic gate generates output Y. Figure 7-38 displays the PLC
ladder logic diagram for Example 7-5.
B
I:0
O:0
I:0
I:0
A
I:0
0000
I:0
2
I:0
I:0
0001
End
Example 7-6
Create the PLC ladder logic diagram for the following Boolean
expression.
Y = A + B + CD + EB
To create the diagram, each rung or each portion of a rung is
created by replacing the Boolean letter with the inputs that match.
Figure 7-39 summarizes the Boolean expressions and ladder diagrams
for the logic gates covered in Sections 7-4 through 7-10.
Figure 7-40 displays the PLC ladder logic diagram. Notice that
inverted A, B, CD, and EB inputs are in parallel (OR). Inputs C and D
are in series (AND). Inputs E and B are also in series (AND).
Example 7-7
A
B
C
D
E
Figure 7-37. Logic gate circuit for Example 7-5.
Create the PLC ladder logic diagram for the following Boolean
expression.
Y = (AB) + AC + BC
Figure 7-41 displays the PLC ladder logic diagram. Notice that
inverted A and B inputs are in series to generate output at the control
relay. Then, the inverted output of AB is in parallel with AC and BC.
Chapter 7
163
164
Example 7-6
OR Gate: Y = A + B
000
I:1/0
O:2/0
A
I:1/1
A
I:0
A + B
Y = A + B + C D + E B
Y
O:0
0000
0
001
NOR Gate: Y = A + B
I:1/0
0
B
I:0
B3:0/0
1
A or B is Inverted
I:1/1
I:0
I:0
B
B3:0/0
O:2/1
A or B is Inverted
I:0
I:0
002
003
AND Gate: Y = A B
I:1/1
I:1/0
004
NAND Gate: Y = A B
I:1/1
I:1/0
O:2/2
Y
CD
EB
0001
End
B3:0/1
Example 7-7
A
B3:0/1
O:2/3
005
006
A
I:0
B
I:0
Control relay
B3:0
0000
XOR Gate: Y = A B + A B
I:1/1
I:1/0
Control relay
B3:0
O:2/4
0
Y
(A B)
Y = (A B) + (A C) + (B C)
O:0
0001
007
I:1/0
I:1/1
XNOR Gate: Y = A B + A B
I:1/1
I:1/0
A
I:1/0
I:1/1
O:2/5
0
A
I:0
I:0
I:0
I:0
AC
BC
0002
End
Chapter 7
165
166
Example 7-9
Example 7-8
Create the PLC ladder logic diagram for the following Boolean
expression.
Y = (A + B) (C + D)
Figure 7-42 displays the PLC ladder logic diagram. Notice that
A is in parallel with B and C is in parallel with D. Then, (A + B) and
(C + D) are in series.
A
I:0
Y
O:0
0000
2
I:0
I:0
0001
D
I:0
Control relay
I:0
B3:0
B + C D
CD
A (B + C D) C
Y = A [A (B + C D) C]
Y
O:0
0
End
Example 7-8
1
C
I:0
0002
Create the logic gate circuit for the PLC ladder logic diagram
displayed in Figure 7-43. First, turn the PLC ladder logic diagram
shown in Figure 7-43 into a Boolean expression as shown in the ladder
C+D
B3:0
0001
Example 7-9
C
I:0
Control relay
In Sections 7.11, 7.12, and 7.13, you learned how to create PLC ladder logic diagrams from truth tables, logic gate circuits, and Boolean
expressions. In this section, you will see the reverse process. You will
use examples to study how to convert PLC ladder logic diagrams to
logic gate circuits. The first step in this process is to find the Boolean expression that represents the ladder logic diagram. You can then
draw the logic gate circuit using the Boolean expression similar. You
can also use the logic converter instrument in the NI Multisim program to find truth tables and Boolean expressions from the logic gate
circuits. Three examples are used to illustrate how to convert PLC ladder logic diagrams to logic gate circuits.
A+B
C
I:0
0000
A
I:0
B
I:0
Y = (A + B) (C + D)
End
Chapter 7
167
168
C
C D + C D
D
CD
B + (C D + C D)
D
B + CD
Y = A [B + (C D + C D)]
B
A (B + CD) C
A
A
[A (B + CD) C]
A
Y = A [A (B + CD) C)
Example 7-10
Create the logic gate circuit for the PLC ladder logic diagram displayed in Figure 7-45. First, turn the PLC ladder logic diagram shown
in Figure 7-45 into a Boolean expression as shown in the ladder diagram. Notice that in rung 0000, inputs C and D in the bottom parallel branches create an XOR logic gate (CD + CD). This is in parallel
(ORed) with input B, forming the following Boolean expression:
B + (C D + C D)
Example 7-11
Example 7-10
A
I:0
I:0
O:0
0000
0
D
C
I:0
I:0
C
I:0
I:0
Y = A [B + (C D + C D)]
B + (C D + C D)
0001
C D + C D
End
Create the logic gate circuit for the PLC ladder logic diagram
displayed in Figure 7-47. First, turn the PLC ladder logic diagram
shown in Figure 7-47 into a Boolean expression as shown in the ladder
diagram. Notice that in rung 0000, parallel (ORed) inputs A, B, and
inverted C are in parallel (ORed) with the output from the control
relay which is in series (ANDed) with inverted input D, forming the
following Boolean expression:
(A + B + C) + [D (A + B + C + D)]
Finally, inverted input E in rung 0001 is in serial (ANDed) with
the output of the control relay. This is equal to the output of Y:
Y = E {(A + B + C) + [D (A + B + C + D)]}
Next, create the logic gate circuit using the Boolean expression
from Figure 7-47. Figure 7-48 displays the logic gate circuit for this
example.
Chapter 7
169
170
Summary
Example 7-11
Control relay
A
I:0
B3:0
0000
0
B
I:0
A + B + C
(A + B + C) + [D (A + B + C + D)]
C
I:0
2
D
Control relay
I:0
B3:0
[D (A + B + C + D)]
Control relay
I:0
B3:0
Y = E {(A + B + C) + [D (A + B + C + D)]}
Y
O:0
0001
0
End
0002
Review Questions
Complete each of the following sentences with the correct word(s).
A
(A + B + C)
B
C
D
(A + B + C) + [D (A + B + C + D)]
(A + B + C + D)
E
Y = E {(A + B + C) + [D (A + B + C + D)]}
E
Chapter 7
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172
30. In an XNOR gate ladder logic diagram, when both inputs are
open, the output is ______.
31. In an XNOR gate ladder logic diagram, when both inputs are
closed, the output is ______.
32. In an XNOR gate ladder logic diagram, when one input is closed
and the other one is open, the output is ______.
33. In a one-rung XNOR gate ladder logic diagram, the normally
closed inputs are connected in ______.
Specify if the following statements are true or false.
34. Both inputs to an AND gate must be high to produce a high
output.
35. Both inputs to a NAND gate must be high to produce a high
output.
36. Inverting a NAND gate will result in creating an AND gate.
37. Only one input to an OR gate must be high to produce a high
output.
38. Both inputs to a NOR gate must be high to produce a high
output.
39. Inverting an OR gate will result in creating a NOR gate.
40. Both inputs to an XOR gate must be high to produce a high
output.
41. Both inputs to an XNOR gate must be high to produce a high
output.
42. All three inputs to a three-input AND gate must be high to
produce a high output.
Create a PLC ladder diagram for the truth tables in the following problems.
43. A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
I
I
I
I
I
I
I
I
I
Y
0
0
0
1
0
1
0
1
Chapter 7
44. A
B
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
C
0
1
0
1
0
1
0
1
I
I
I
I
I
I
I
I
I
173
174
Create a relay logic diagram for the ladder diagrams in the following problems.
Y
0
0
0
1
0
1
1
0
47. L1
L2
A
CR
B
C
E-1
Create a PLC ladder diagram for the relay logic diagrams in the following
problems.
45.
CR
E-2
A
B
C
D
E
F
48. L1
L2
Y1
G
H
C
Y1-1
D
Y1-2
Y2
46. A
B
Y2-1
C
D
E
Create a PLC ladder diagram for the Boolean expressions in the following
problems.
49.
50.
51.
52.
Y = (A + B) + (A + B + C)
Y = ABC + AB + ABC
Y = B(A + C) + C(A + B) + AC
Y = (AB + AB) (AB + AB) + ABC