PLC Logic and Bit Shift

Instructions
IChapter Outline
13.1 Introduction
13.2 Logic Gate Instructions
13.3 Shift Left Instruction
13.4 Shift Right Instruction
13.5 LogixPro Simulator Examples

ITechnical Terms
bit shift left (BSL) instruction control register (R6)
bit address reset (RES) instructions
length bit shift right (BSR) instruction

| Learning Objectives
After completing this chapter, you will be able to:
• Use the NOT instruction in PLC ladder logic diagrams.
• Use the AND instruction in PLC ladder logic diagrams.
• Use the OR instruction in PLC ladder logic diagrams.
• Use the XOR instruction in PLC ladder logic diagrams.
• Program the NOT instruction with AND, OR, and XOR
instructions to create NAND, NOR, and XNOR instructions.
• Create a PLC ladder logic diagram that uses the bit shift left
(BSL) instruction.
• Create a PLC ladder logic diagram that uses the bit shift right
(BSR) instruction.
• Open a data file bit dialog box to monitor the operation of a bit
shift right or a bit shift left instruction.
• Reset the bit shift left or the bit shift right instruction to its
starting bit position.

113.1 Introduction
In Chapter 1, you learned how to create PLC ladder logic diagrams
to perform operations of digital logic gates. These logic gates you
explored were the NOT, AND, NAND, OR, NOR, XOR, and XNOR.
275
276 Programmable Logic Controllers: Hardware and Programming

Allen-Bradley SLC 500 series programmable logic controllers

have four logic gate instructions: NOT, AND, OR, and XOR. In this
chapter, you will learn how to use these four instructions to perform
the operations of logic gates for the sixteen-bit data bit files in a PLC
system.
There are two groups of internal bit data files in the SLC 500 PLC
system. These data bit files are B3 and BIO. Each data bit file contains
256 words. This means that Allen-Bradley SLC 500 series PLCs have
B3:0 through B3:255 and B10:0 through B10:255 internal 16-bit words.
Therefore, SLC 500 series programmable logic controllers have 512
internal 16-bit words for a total of 512 x 16 = 8,192 bits. Each internal
bit can be used to control one internal coil. The contacts associated
with these internal coils are used to turn on or turn off output devices.
Notice that data bit files are referred to by B3 or B10 labels. However,
each bit in the data bit file is labeled independently (e.g., B3/1, B3/2,
B10/1, and B10/2). It should also be noted that one can reference each
bit as B3/17 or B3:l/1. B3/17 means that you want to use the 17thbit in
file B3 which is the same as bit one in word B3:l (i.e., B3:l/1).
In this chapter, you will also learn how to use the bit shift instruc­
tions of a PLC device to rotate bits through an internal bit data file.
Allen-Bradley SLC 500 series PLCs have two bit shift instructions.
These bit shift instructions are bit shift left (BSL) and bit shift right
(BSR). In this chapter, you will learn how to use these instructions in
ladder logic diagrams.

113.2 Logic Gate Instructions

Allen-Bradley SLC 500 series PLCs have four logic gate instruc­
tions: NOT, AND, OR, and XOR. Figure 13-1 displays the logic gate
instructions. The instructions carry out the operation for sixteen-bit
internal bit data file words.
As discussed in Chapter 1，the NOT, or invert, instruction converts
a logic high (1)to a logic low (0) and vice versa. The AND instruction
generates a logic low (0) whenever one of the corresponding bits is 0.
The OR instruction generates a logic high (1)whenever at least one of
the corresponding bits is 1 .The XOR instruction generates a logic high
(1 )whenever the two corresponding bits in the word do not match.
Figure 13-2 displays the 16-bit words in bit data file B3 used for the
logic instructions displayed in Figure 13-1. Input words and the result
of the logic instructions' operations are displayed in Figure 13-2. fo r
example, the result of logical AND for data words B3:2 and B3:3 are in
the data word B3:4.
The NAND, NOR, and XNOR logic instructions are built by
inverting the AND, OR, and XOR instructions respectively. Exam­
ine Figures 13-3,13-4, and 13-5. These figures display how to cre­
ate NAND, NOR, and XNOR logic instructions respectively. After
 Chapter 13 PLC Logic and Bit Shift Instructions 277

------- NOT ------

oooo NOT
Source B3 ：
0
1111111100000000<
Dest B3:1
0000000011111111<

------- AND ------

0001 Bitwise AND
Source A B3:2
AAAAh<
Source B B3:3
00FFh<
Dest B3:4
00AAh<

-------OR --------
0002 Bitwise inclusive OR
Source A B3 :5
5555h<
Source B B3:6
FF00h<
Dest B3:7
FF55h<

-------XOR -------
0003 Bitwise exclusive OR
Source A B3 :8
CE3Ch<
Source B B3 :9
6EF2h<
Dest B3:10
A0CEh<

0004 〈 End 〉

Figure 13-1. T he four logic instructions for A llen -B rad le y SLC 500 series PLCs.

a logic instruction is executed, the status bits in the status file are
updated. The status bits are in word S2:0 bits 0-3 in the processor
status file (S2). Descriptions of these bits are listed below.
Status Bit Description
S2:0/0 Carry (C)
S2:0/l Overflow (O)
S2:0/2 Zero (Z)
S2:0/3 Sign (S)
278 Programmable Logic Controllers: Hardware and Programming

D a ta File B 3 (b in ) BINARY
Of f s e t
B3 0
15 14 13 12 11 10
1 1 1 1 1 1
9
1
8
1
7
0
6
0
5
0
4
0
3
0
2
0
am
0 0
：
E ：i 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B3 2 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
B3 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B3 4 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0
B3 5 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1
B3 6 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
B3 7 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1
B3 8 1 0 0 1 1 1 0 0 0 1 1 1 1 0 0
B3 9 0 1 0 1 1 1 0 1 1 1 1 0 0 1 0
B3 10 1 0 1 0 0 0 0 0 1 1 0 0 1 1 ID
^JJ jlE
jB3:10/0 ニニ— ニ ニニ ] Radix:I Binary ]
Symbol: | ] Columi 1J
D esc:[
Properlies
J Usage | Help
J
Figure 13-2. B inary bit data files for the logic
instructions show n in Figure 13-1.

-AND
0000 Bitwise AND
Source A B3:0
AAAAh<
Source B B3:l
00FFh<
Dest B3:2
00AAh<

■NOT
0001 NOT
Source B3:2
0 0 0 0 0 0 0010101010 <
Dest B3：3
1 1 1 1 1 1 1101010101 <

0002 End

Figure 13-3. AN D and N O T instructions can be com bined to create a NAN D instruction.

Example 13-1
For this example, assume that an expanded chassis SLC 503
PLC has two input modules (1:1/0 and 1:2/0) and one output module
(0:3/0). A logic one output must be generated whenever values of two
input ports do not match. In an Exclusive OR instruction, the output
is high if one input is low and the second one is high. Figure 13-6
displays the PLC ladder logic diagram for Example 13-1.
 Chapter 13 PLC Logic and Bit Shift Instructions 279

------- o r --------
oooo Bitwise Inclusive OR
Source A B3:0
5555h<
Source B B3:l
FF00h<
Dest B3:2
FF55h<

■NOT
0001 NOT
Source B3:2
1 1 11111101010101 <
Dest B3:3
0 0 0 0 0 0 0 010101010 <

0002 :End>

Figure 13-4. Using an OR and a N O T instruction to create a NOR instruction.

------- XOR -------

0000 Bitwise exclusive OR
Source A B3:0
CE3Ch<
Source B B3:l
6EF2h<
Dest B3:2
A0CEh<

-NOT
0001 NOT
Source B3：2
10 1 0 0 0 0011001110 <
Dest B3:3
0 101111100110000 <

0002 End

F ig u re 13-5. Using an XO R and a N O T instruction to create an X N O R instruction.

Figure 13-7 displays the input and output files for Example 13-1.
The output files are created from the assumed input files.

p i3_3 Shift Left Instruction

PLC shift instructions are often used to control display signs in a
plant or outside. A flashing arrow display showing that one lane in a
highway is closed due to construction is one example. It can easily be
constructed with a PLC bit shift instruction.
280 Programmable Logic Controllers: Hardware and Programming

Example 13-1
■XOR
0000 Bitwise exclusive OR
Source A 1:1.0
C717h<
Source B 1 :2 . 0
658Eh<
Dest 0:3.0
A299h<

0001 End

Figure 13-6. PLC ladder logic diagram fo r Exam ple 13-1.

m Jnlxl
r~— ■■■■ -—
————
...■■■■■ ■■1 ■■ 1

■ 1 :2 . 0 1 0 1
。 。
_。… …
0 0 0 1 0 1 0 0 0
…
1 1 1
ぜ
0

D a ta File 0 0 (bin) -Inlxl

O ffse t 15 14 13 12 1 1 1 0 9 8 7 6 5 4 3 2
—
jJJ ______
10:3/0 コRadix:卜 V J
Symbol:匚 ]
Desc:匚
网 i l .^Properties J ysage^J 一Forces^| Help

Figure 13-7. Input and output files for Exam ple 13-1.

Bit shift left (BSL)
instruction:
Instruction that shifts the
bits in the data file to the
left once for every low-
to-high transition on its
input.
Bit address:
Parameter in the BSL
and BSR instructions
that indicate the starting
bit position.
Length:
Parameter in the BSL
and BSR instructions
that indicate the number
of bits to be shifted.
Figure 13-8 displays the ladder diagram of a bit shift left instruc­
tion for the Allen-Bradley SLC 500 series PLC. When a b it s h ift le ft
(BSL) in struction is energized, it shifts a bit to the left for every pro­
gram scan. In this example, the input pushbutton is used to energize
the bit shift left instruction. Therefore, the pushbutton must be pressed
to energize the BSL instruction.
The B3 or B10 file can be used to contain the bits to be shifted. In
Figure 13-8, bit data file B3 contains the bits. The b it ad d ress for a BSL
instruction is the bit in the starting position. The number of bits that
are shifted determines the length. The bit where the last shifted bit
exits is called the unload bit.
In Figure 13-8, the bit address is B3/0 or B3:0/0 and the length is
seven. Therefore, bits B3/0, B3/1, B3/2, B3/3, B3/4, B3/5, and B3/6 are
shifted to the left. The last bit (the bit address) exits and can reenter
at the bit on the beginning of the length (B3:0/0). This is done if you
have instructions similar to that in rung 0002 of the ladder logic dia­
gram in Figure 13-8. Note that the unload bit (R6:0/UL) is placed onto
bit B3:0/0.
 Chapter 13 PLC Logic and Bit Shift Instructions 281

Bit Shift Left (BSL) Instruction

M OV ■
0000 ヨE Move
Source 43690
AAAAh
Dest #B3:0
Length 43604

BSL ■
0001 Bit shift left <EN>
File #B3:0
Control R6:0
Bit Address B3:0/0
Length フ

0002

0003 ヨE :s>

0004

Figure 13-8. Bit shift left (BSL) instruction fo r the A llen -B rad le y SLC 500 PLC.

In the bit shift left instruction, a control register must be used to

hold the status flag bits. PLCs use the status flag bits in control regis­
ters to monitor and control the shift instruction. Registers in data file
con trol register (R6) are used as control registers. These control reg­ Control register (R6):
isters are R6:0 through R6:255. Therefore, Allen-Bradley SLC 500 PLCs Holds status flag bits.
have 256 control registers.
In Figure 13-8, register R6:0 is the control register. In the control
register, two status bits are available to the PLC programmer. These
bits are the enable bit (R6:0/EN) and the done bit (R6:0/DN). The
enable coil (R6:0/EN) is energized when the BSL instruction is on.
The done coil (R6:0/DN) is energized when the BSL instruction has
shifted all bits as specified by the length. The contacts associated with
these bit coils can be used to turn on or turn off other PLC instructions
or output devices.
The reset (RES) in struction can be used to reset the BSL instruc­ Reset (RES)
instruction:
tion. In Figure 13-8, the reset button is energized when switch 1:1/2 is
An instruction used with
closed. Then, the BSL instruction resets to position zero. Example 13-2 bit shift instructions to
illustrates how to use the BSL instruction in ladder logic diagrams. reset to the original bit.
282 Programmable Logic Controllers: Hardware and Programming

Example 13-2
In this example, an ON-delay timer is used to control the speed of
the operation of a BSL instruction. Figure 13-9 displays the PLC lad­
der diagram for Example 13-2. Placing a one in bit address B3/0 of the
data bit file causes the green pilot light (Green_PLT) to turn on. Then,

Example 13-2
This program will turn each light on then off every three seconds.

Switch T4:0
-

------ TON-----
:
_Ed

0000 Timer ON Delay <EN>

Timer T4 ：0
Time base 0.1
Preset 30
Accum 0
: E

T4 -------BSL-------
0001 Bit shift left
File #B3:0
Control R6:0
Bit addressB3:0/0
Length 4

B3:0
0002 ベ > -
0
Green_PLT
B3
E

0003 ヨ O

White一PLT

0004 ヨ o
Red_PLT
: E
i

0005 o
m

0006 ヨE 〈 RES〉

0007

Figure 13-9. PLC ladder logic diagram for Example 13-2.

 Chapter 13 PLC Logic and Bit Shift Instructions 283

the bit shift left (BSL) instruction rotates this high bit through B3/0,
B3/1, and B3/2 in order to turn on the white pilot light (White_PLT),
red pilot light (Red_PLT), and then again the green pilot light (Green_
PLT) every 3 seconds. Figure 13-10 displays the bit data file B3:0.
When the PLC starts operating, the green pilot light (Green_PLT)
turns on. Closing the switch in rung 0000 starts the timer. After three
seconds, the timer done status coil (T4:0/DN) energizes. Then, the
normally closed contact in rung 0000 (T4:0/DN) opens and the nor­
mally open contact in rung 0001 (T4:0/DN) closes.
When the normally closed contact in rung 0000 opens, the non-
retentive timer ON-delay zero (T4:0) resets the content of its accumulated
register to zero (T4:0.ACC = 0). When the normally open contact in rung
0001 closes, the BSL instruction shifts the bit in B3/0 to the left.
Now the B3/1 bit is high. Therefore, the white pilot light
(White_PLT) turns on.
Notice that the non-retentive timer ON-delay (T4:0) resets when
normally closed contact (T4:0/DN) opens. After another three sec­
onds, the timer done coil (T4:0/DN) energizes again. Then, the BSL
instruction shifts the bits to the left once more. Now, the red pilot light
(Red_PLT) turns on and the white pilot light (White_PLT) turns off.
Consequently, each of the pilot lights (0:2/0, 0:2/1, and 0:2/2)
turns on in sequence for three seconds. After four bits shift left, the
normally open contact (R6:0/DN) closes and resets the BSL instruc­
tion. Now, the green pilot light (0:0/0) turns on. The process continues
until the switch in rung 0000 is opened to stop the timer instruction.
Closing the normally open pushbutton in rung 0005 can also reset the
BSL instruction.

,1 3 .4 Shift Right Instruction

Operation of the bit shift right instruction is similar to the opera­
tion of the bit shift left instruction. When a b it s h ift right (BSR) Bit shift right
in struction is energized, it shifts a bit to the right for every program (BSR) instruction:
Instruction that shifts the
bits in the data file to the
right once for every low-
to-high transition on its
input.
D a ta File B 3 (bin) jn jx j
........
：O f f s e t 15 14 13 12 1 1 1 0 9 8 7 6 5 4
B 3 :0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 1:1 0 葡

J jj
IEl3:0/0 コ Radix: binary
Symbol :匚 コ 厂 」
|B3 Properties 1 Usage Help

Figure 13-10. Bit data w ord B 3:0 is used in the

bit shift left instruction.
284 Programmable Logic Controllers: Hardware and Programming

scan. Figure 13-11 displays the schematic diagram of a BSR instruc­

tion for the Allen-Bradley SLC 500 series PLC.
Whenever the input pushbutton in rung 0001 is pressed, the data
bits in file B3:0 are shifted to the right. This means that the pushbut­
ton must be pressed to energize the B^R instruction. The length of
the data bit file shown in Figure 13-11 is six. Therefore, for each low-
to-high input, bits B3/5, B3/4, B3/3, B3/2, B3/1, and B3/0 are shifted
to the right once. The last bit (B3/0) exits and reenters at the bit on the
beginning of the length (B3/5). This is done by placing the unload bit
(R6:1/UL) in (B3:0/5).
The done coil in control register (R6:1/DN) is energized when the
instruction has shifted the bits six times. Similar to the bit shift left
instruction, the reset (RES) instruction in rung 0003 resets the bit shift
right instruction to position zero. Example 13-3 illustrates how to use
the BSR instruction in PLC ladder logic diagrams.

Bit Shift Right (BSR) Instruction

Move
0000 ェ 1 ------- MOV---------
r Move
し
Source 43690
AAAAh
Dest #B3:0
32

PB
in 丄

0001 r Bit shift right

し
File #B3:0
Control R6:1
Bit address B3:0/5
Length 6
6F P U

R6
J Jし

:1
0002
J
C
I

R
e
ェS :
l l

et
Jj2

0003

0004 - C End J -

Figure 13-11. Bit shift right (BSR) instruction for the Allen-Bradley SLC 500 PLC.
 Chapter 13 PLC Logic and Bit Shift Instructions 285

Example 13-3
Figure 13-12 displays the PLC ladder logic diagram for Exam­
ple 13-3. Figure 13-13 displays the bit data file for Example 13-3.
Notice that bit three (B3/3) is set to one.

Example 13-3

Switch T4:0
,E

----- TON------
0000 Timer On Delay
Timer T4:0
Time base 0.1
Preset 40
Accum 0
彐

T4 :0
E

•BSR •
0001 Bit shift right
File #B3:0
Control R6:0
Bit address B3:0/3
Length 4
R
6

:
C
E

B3:0
■ ■■
rp

0002
< >
3
Green PLT
B
3

:0
E-
o
r3

0003
p

IO
3

E-

Red_PLT
B
3

o
r3

0004
p2

癒 ite_PLT
B3:0
0005 (RES 〉
1
Reset
1:1
0006 (RES 〉
1

0007 (END 〉

Figure 13-12. PLC ladder logic diagram for Example 13-3.

286 Programmable Logic Controllers: Hardware and Programming

D a ta File B 3 (b in ) BINARY
IOf f 7 e t 15 14 13 12 1 1 1 0 9 8 7 6 5 4 3 2 1 EK

A J

旧 3:0/3 Radix:|*Binary
Symbol:[ 「」
D esc:[
Properties Usage Help

Figure 13-13. Bit data file fo r E xam ple 13-3.

When the PLC starts operating, all the lights are off. Closing the
switch in rung 0000 starts the timer. After four seconds, the timer done
status coil (T4:0/DN) energizes. Then, the normally closed contact in
rung 0000 (T4:0/DN) opens and the normally open contact in rung
0001 (T4:0/DN) closes.
When the normally closed contact in rung 0000 opens, the non-
retentive timer ON-delay zero (T4:0) resets the content of its accumu­
lated register to zero (T4:0.ACC = 0). When the normally open contact
in rung 0001 closes, the bit shift right instruction (BSR) shifts the bit
B3/3 to the right.
Now, the bit B3/2 is high. Therefore, red pilot light (Red_PLT)
turns on.
Notice that the non-retentive timer ON-delay (T4:0) resets when
normally closed contact (T4:0/DN) is opened. After another four sec­
onds, the timer done coil (T4:0/DN) energizes. Then, the BSR instruc­
tion shifts the bits to the right once more. Now, the white pilot light
(White_PLT) turns on and the red pilot light (Red_PLT) turns off.
Following the pattern, you can see that each of the output lights
(0:2/0,0:2/1, and 0:2/2) will turn on sequentially for four seconds. Then,
all the outputs turn off and the process continues until the switch in rung
0000 is opened to stop the timer instruction. Closing the normally open
reset pushbutton in rung 0006 can also reset the BSR instruction.

■ 13_5LogixPro Simulator Examples

Example 13-4
The diagram in Figure 13-14 shows the programming for a rotat­
ing bit shift left function. Pressing the pushbutton at address 1:1/0
shifts the bits in file #B3 to the left once. Closing the switch at address
1:1/1 will generate pulses with a one-second duty cycle that will auto­
matically shift the bits in file #B3 to the left once every one-second
time interval. Closing the switch at address 1:1/2 re-enters the unload
bit (R6:0/UL) to the beginning bit address in file #B3. This unloading
 Chapter 13 PLC Logic and Bit Shift Instructions 287

and moving of the bit creates a rotate bit left function. The re-entry
process or file #B3 is displayed in the binary table in Figure 13-14.
Pressing the pushbutton at address 1:1/3 resets the control register
R6:0 and sets the bit pointer to the beginning location B3:0/0.

Bit Shift Left (BSL); Bits are shifted to the left starting from B3:0/0 to B3:0/7.
1 :1 / 0 BSL-----------
000 Bit Shift Left —
Manual-Shift Pushbutton File #B3:0
Control R6 ：0
T4:0/DN
Bit Address B3 :0/0
< DN> -
Length 8

Close input 1:1/1 to create an automatic BSL.

1:1/1 T4:0/DN ■TON ■
001 う E----- Timer On Delay <EN>
Auto-Shift Mode Timer T4:0
Time Base 0 ：1
Preset 10
Accum 5

The bit on the far left-hand side (B3:0/7) controls the light (0:2/0).
B3:0/7 0 : 2/0
002
— ] 卜
Y-LT

**Close input 1:1/2 to re-enter the lost bit that comes out of the left
side (in this case B3:0/8). Therefore, creating Rotate Left.
1 : 1/2 R6:0/UL B3:0/0
003
Rotate Mode Rotate Entry Location

1:1/3 R6:0
004 -3 E- <R ES>
Reset
005 End
Lost bit re-entered
I xj

d
Radix: [Binary Table: |B3: Binary jJ ___h . - . ^ j

Figure 13-14. PLC ladder logic diagram and binary table for Exam ple 13-4. P rogram m ing the bit shift
left (BSL) function in the LogixP ro simulator.
288 Programmable Logic Controllers: Hardware and Programming

Example 13-5
The diagram in Figure 13-15 demonstrates how to use a timer
on delay (TON) function and a bit shift left (BSL) function to turn on
and off lights in ascending order every three seconds. The timer on
delay controls the bit shift left function, which moves a bit through

1 :1 / 0 T4:0/DN •TON ■
000 Timer On Delay くE N >
Start Timer T4:0
Time Base 0.1 <DNト
Preset 30
Accum 6

T4-.0/DN BSL-----------
001 Bit Shift Left <EN>
File #B3:0
Control
Bit Address
R6:0
B3 :0/0
<™>
Length 4

R6:0/UL B3:0/0
002

B3: 0 / 0 0 :2/0
003

B3:
004

B3:0/2 0 :2/2
005
RLT

1 :1/1 R6:0
006
Reset
007 End^)—

s :r . j <i
15 14 13 12 1 1 1 0 9 8 7 6 5 4 3 2 1 0
B3:0/ o o o 1 o o o 1 o o o 1 o o o 1 I

Radix: [Binary J Table: |B3: Binary 一 .-:：

〖
f e e s 」 昼】

Address | Symbol |

Figure 13-15. PLC ladder logic diagram and binary table fo r Exam ple 13-5. Using the bit shift left
fu nctio n to turn on and o ff three lights in ascending order.
 Chapter 13 PLC Logic and Bit Shift Instructions 289

the positions of B3:0. Lights connected to the outputs at addresses

0:2/0, 0:2/1, and 0:2/2 illuminate when a bit is rotated into their
corresponding binary position: B3:0/0, B3:0/l, and B3:0/2. Lights first
turn on and then off in ascending order. This process continues until
the start switch at address 1:1/0 is opened. The reset pushbutton at
address 1:1/1 is used to reset the control register R6:0 and set the bit
pointer to the beginning location B3:0/0.

Example 13-6
The diagram in Figure 13-16 shows the programming for a rotat­
ing bit shift right function. Pressing the pushbutton at address 1:1/0
shifts the bits in file #B3 to the right once. Closing the switch at address
1:1/1 will generate pulses with a one-second duty cycle that will auto­
matically shift the bits in file #B3 to the right once every one-second
time interval. Closing the switch at address 1:1/2 re-enters the unload
bit (R6:0/UL) to the beginning bit address in file #B3. This unloading
and moving of the bit creates a rotate bit right function. The re-entry
process of file #B3 is displayed in the binary table in Figure 13-16.
Pressing the pushbutton at address 1:1/3 resets the control register
R6:0 and sets the bit pointer to the beginning location B3:0/7.

Bit Shift Right (BSR); Bits are shifted to the right starting from B3s0/7 to B3:0/0.
ェ：
1/0 ---- BSR-----------
000 Bit Shift Left <EN>
Manual Mode Pushbutton File #B3:0
T4:0/DN Control
Bit Address
R6:0
B3:0/7
<DN>
Length 6

Close input 1:1/1 to create and automatic BSR.

1 :1 / 1 T4:0/DN TON-
001 Timer On Delay <™>
Auto-Shift Mode Timer T4 ：
0
Time Base
Preset
0:1
10
<DN>
Accum 9

The bit on the far right-hand side (B3:0/0) controls the light (0:2/0).
2

B3 ：
0/0 0:2/0
: / 0
>
ぐ

G-LT

(Continued)
Figure 13-16. PLC ladder logic diagram and binary table fo r Exam ple 13-6. P rogram m ing the bit
shift right (BSR ) fu nctio n in the LogixP ro sim ulator.
290 Programmable Logic Controllers: Hardware and Programming

Radix: [Binary Table: [B3: Binary 眷

Address 丨 Symbol |

Figu } 13-16. C ontinued.

Example 13-7
The diagram in Figure 13-17 demonstrates how to use a timer on
delay (TON) function and a bit shift right (BSR) function to turn on and off
lights in descending order every two seconds. The timer on delay controls
the bit shift right function, which moves a bit through the positions of
B3:0. Lights connected to the outputs at addresses 0:2/0, 0:2/1, and
0:2/2 illuminate when a bit is rotated into their corresponding binary
position: B3:0/0, B3:0/l, and B3:0/2. Lights first turn on and then off
in descending order. This process continues until the start switch at
address 1:1/0 is opened. The reset pushbutton at address 1:1/1 is used
to reset the control register R6:0 and set the bit pointer to the begin­
ning location B3:0/7.
 Chapter 13 PLC Logic and Bit Shift Instructions 291

: E
T4:0/DN

彐
TON-----------
000 Timer On Delay <EN>
Start Timer T4 ：
0
Time Base 0.1
Preset 20
Accum 5

T4:0/DN ■BSR •
0 01 Bit Shift Right
File #B3:0
Control R6:0
Bit Address B3:0/3
Length 4

B3:0/3
002

2
B3 o
:

c
/o

フ
003 -]E
GLT

B3 0 : 2/ 1
004 -]E
RLT
B3:0/2 0 :2/2
005
WLT

R6:0
006 -3 B <R ES>
Reset
007 End

E B 3 S S 9 H H H H IH B . 凶
15 14 13 12 1 1 1 0 9 8 7 6 5 4 3 2 0
B3:0/ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 。J
Radix: [Binary Table: [OS: Binary |
_

Address f Symbol \

Figure 13-17. PLC ladder logic diagram and b inary table for Exam ple 13-7. Using the bit shift right
function to turn on and o ff three lights in descending order.
Programmable Logic Controllers: Hardware and Programming

Summary
• The NOT instruction converts a bit file word's bits from a logic
high (1)to a logic low (0), and vice versa.
• The AND, OR, and XOR instructions perform logic operations
on the bit of two data source locations and place the outcome in
a destination location.
• The bit shift left (BSL) instruction shifts left a specified number
of bits in a file; the bits are shifted one position every time the
instruction is energized.
• The bit shift right (BSR) instruction shifts right a specified
number of bits in a file; the bits are shifted one position every
time the instruction is energized.
• Bit shift instructions (BSL and BSR) are typically used to control
lights on a display board.

Review Questions
1 . How many control registers are available in an Allen-Bradley
SLC 500 PLC? Name them.
2. Which coil is energized to indicate that a bit shift left (BSL) has
shifted the bits as many times as indicated in the length?
3. Which data file(s) are ordinarily used for bit shift instructions?
4. How can a bit shift instruction be brought to its beginning or
original position?
5. What instruction can be used to reset a bit shift instruction?
6. When is the control bit R6:0/EN in a bit shift instruction
energized?
7. What input transition causes the bit shift right (BSR) instruction
to shift the bits once?

Complete each o f the following sentences with the correct word(s).

8. In bit shift instructions, data file or can hold the
bits, which are to be shifted.
9. The bit where the first shifted bit exits is called th e .
10. T h e determines the number of bits to be shifted.
1 1 .Words through can be used for control registers in
the bit shift instructions.
12. For every low-to-high input switch transition on the bit shift left
(BSL) instruction, data bits will sh ift once.
13. In a bit shift right (BSR) instruction that uses the R6:0 control
register, the enable bit is addressed a s .
 Chapter 13 PLC Logic and Bit Shift Instructions 293

14. The enable coil i s when a normally open input switch to

the bit shift right (BSR) instruction is closed.
15. In a bit shift right (BSR) instruction that uses the R6:0 register,
the done co il is energized when the BSR instruction has
shifted all the bits as specified by the length.
16. T h e bit must be used to bring the BSR instruction
position to the start position.
17. For every low-to-high input switch transition on the bit shift
right (BSR) instruction, data bits will sh ift once.

Specify if the following statements are true or false.

18. You may use registers R6:0 through R6:255 for control registers
in bit shift instructions.
19. The R6:0/DN bit can be used to reset the BSL instruction.
20. Usually, the N7 data file holds the bits for the bit shift left (BSL)
instruction.
2 1 . Usually, the B3 data file holds the bits for the bit shift right (BSR)
instruction.
22. The BIO data file can hold the bits for the bit shift left (BSL)
instruction.
23. The R6:0/EN is energized when the input to the bit shift left
(BSL) is closed.
24. The reset (RES) instruction is used to reset the BSL and BSR
instructions.
25. Usually the T4:0/DN contact of a timer ON-delay instruction is
used as an input instruction to bit shift instructions.
294 Programmable Logic Controllers: Hardware and Programming

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Learning new fu nctio ns through te xtb o o k exam ples is im portant; however, students should also
independently im agine and te st other p ossible fu nctio n applications. S tart with fa m iliar fu nctio ns and
m odify inputs, specifications, and ladder program m ing. O bserve and record changes in the outputs and
data tables. These activities w ill cultivate a deeper understanding of PLC operation and capabilities.