IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO.

8, AUGUST 2013

4051

A New Control Method of Interleaved Single-Stage

Flyback ACDC Converter for Outdoor LED
Lighting Systems
SangCheol Moon, Student Member, IEEE, Gwan-Bon Koo, and Gun-Woo Moon, Member, IEEE

AbstractIn outdoor light-emitting diode (LED) lighting systems, there are a lot of applications. Depending on the output
power rating, the power stage to drive an LED can be classified
into single-stage and two-stage structures. The single-stage structure is for low-power LED lighting applications. However, it is
difficult to apply at over 6070 W of output power because of its
low efficiency and huge transformer at high power. On the other
hand, the two-stage structure is usually used for high power applications. However, it is undesirable to cover wide output power
range because of its poor power factor (PF) under the light load
condition. To solve these problems, this paper proposes a new pulse
duty cycle control method with pulse frequency modulation for
an interleaved single-stage flyback acdc converter. The proposed
converter provides high efficiency under heavy loads with low ac
line condition and under light loads with high ac line condition.
In addition, the proposed converter shows high PF and low total harmonic distortion even when the output power is very low.
As a result, a single LED acdc converter can cover wide power
range for outdoor LED lighting applications. To verify the validity
of the proposed converter, an 81-W prototype converter has been
implemented and experimented on.
Index TermsFrequency control, interleaved flyback, lightemitting diode (LED), power factor correction (PFC), single-stage,
total harmonic distortion (THD).

I. INTRODUCTION
OWADAYS, the use of high-brightness light-emitting
diode is increasing in a lot of outdoor lighting applications
such as street lights, floodlights, beacon lights, tunnel lights, and
security lights, because of its high luminous efficacy, ease to
drive, the absence of a mercury problem and long lifetime. The
output power of these applications is usually around 10200 W.
Since outdoor lights are usually supplied by an ac source, they
have to comply with the IEC61000-3-2 standard [1] regarding

Manuscript received June 8, 2012; revised August 31, 2012 and October 9,
2012; accepted November 4, 2012. Date of current version January 18, 2013.
This work was supported by the National Research Foundation of Korea funded
by the Korea Government (MEST) under Grant 2012-0000981. This work was
presented at the 27th Annual IEEE Proceedings of the Applied Power Electronics Conference and Exposition, Orlando, FL, Feb. 5 to 9, 2012. Recommended
for publication by Associate Editor J. M. Alonso.
S. Moon and G.-W. Moon are with the Department of Electrical Engineering,
Korea Advanced Institute of Science and Technology, Daejeon 305-701, Republic of Korea (e-mail: caprio@angel.kaist.ac.kr; gwmoon@ee.kaist.ac.kr).
G.-B. Koo is with the Fairchild Korea Semiconductor, Ltd., Bucheon 420711, Korea (e-mail: gwanbon.koo@fairchildsemi.com).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2012.2229471

Fig. 1. Power stage of LED driver. (a) Single-stage structure. (b) Two-stage
structure.

harmonic content and power factor (PF). The PF is required that

is higher than 0.9, and the total harmonic content has to meet the
IEC61000-3-2 Class C lighting equipment standard. Recently,
the total harmonic distortion (THD) of less than 10% is required
in the industry.
In outdoor lighting systems, according to the output power rating, the power stage to drive an LED can be classified into singlestage [2][8] and two-stage structures. As shown in Fig. 1(a), the
single-stage structure for an LED power supply unit combines
the power factor correction (PFC) part and the dcdc converter
part into one stage. As shown in Fig. 1(b), in the two-stage
structure, the first stage is the acdc converter for PFC and the
second stage is the dcdc converter for regulating the output
voltage or current. A critical conduction mode (CRM) boost
converter is widely used for the first stage and forward, flyback,
half- bridge and LLC converters are used for the second stage
because they have high PF and efficiency. In two-stage structure, two power stages can be controlled separately so that it
is easy to optimize and it can handle high power applications.
In addition, since the LED current ripple caused by the ac line
source is very small, there is no invisible flicker problem detected by digital devices such as digital cameras. However, the
two-stage structure needs a large number of components and
two kinds of control ICs so that it costs a lot and shows low
efficiency due to the two processes of the input power. Since the
output voltage of the PFC circuit is around 400 Vdc , a very high
voltage rating electrolytic capacitor is required for the bulky
capacitor resulting in a reduction in both the lifetime and the
reliability. Especially, in the CRM boost converter for PFC,
it shows poor PF and THD under light load condition due to
the negative drain current for valley switching. Therefore, the

0885-8993/$31.00 2012 IEEE

4052

Fig. 2.

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013

Interleaved single-stage flyback converter.

two-stage structure cannot cover the wide output power range

of LED lighting applications.
On the other hand, the single-stage structure has a low component count, a low cost, a simple control circuit, and high
efficiency. Since there is no high voltage rating electrolytic capacitor for boost output voltage, single-stage has a long life and
high reliability compared with two-stage structure. A CRM flyback converter is widely used as the single-stage structure due
to its high efficiency by valley switching even if it still shows
poor PF and THD under light load condition due to the valley
switching of the CRM control method. On the other hand, a
DCM flyback converter shows good PF and THD, but it has low
efficiency due to its high rms current. Most single-stage flyback
converters are hard to apply at over 6070 W LED applications,
because the flyback converter usually has low efficiency and a
huge transformer with high power applications. The single-stage
structure also cannot cover wide output power range. To handle
high output power with the flyback topology, an interleaving
control method is a possible solution [9][15].
As shown in Fig. 2, the interleaving control method provides
small input and output filters, low voltage stress on the main
switch and a low profile design when compared to noninterleaving methods. While the CRM interleaved flyback converter
has high efficiency, but shows poor PF and THD under light
load condition, the discontinuous conduction mode (DCM) interleaved flyback converter has good PF and THD under light
load condition, but shows low efficiency due to its high rms
current. To achieve high efficiency and good PF and THD in
wide output power range, this paper proposes a pulse duty cycle
pulse frequency modulation (PDPFM) control method for an
interleaved single-stage flyback (ISSF) converter.
II. PROPOSED CONTROL METHOD
The proposed control method adopts DCM operation which
can achieve high PF for wide output power range. In the proposed method, the interleaved DCM flyback converter is basically controlled by frequency modulation, not pulsewidth modulation (PWM). As shown in (1), the turn-ON time corresponds
to the switching frequency to reduce the frequency variation and

Fig. 3.

Key waveforms of the proposed control method.

to achieve high efficiency

Ton = m fsw

(1)

where m is a constant. For low conduction loss under heavy load

with low ac line condition, the proposed method increases the
switching frequency and the turn-ON time. On the other hand, to
reduce the switching loss under light load with high ac line, the
proposed method decreases both the switching frequency and
the turn-ON time. Therefore, in Fig. 2, average output power
over half of the ac line period can be expressed as
Po =

2
m D fSW
Vline
Lm 1

(2)

where Vline is the ac line voltage in rms, is efficiency, D is

duty cycle, and Lm 1 equals Lm 2 . Output power is controlled by
duty cycle and switching frequency. As a result, the proposed
converter can achieve high PF and low THD by utilizing DCM
operation, and high efficiency due to frequency modulation in
wide output power range.
A. Operation Principle
Fig. 3 shows the key waveforms of an interleaved DCM flyback converter with the proposed method. The switching period
is subdivided into six modes. Since operation modes 13 are
similar to modes 46, only the first three operation modes are
presented. The main equivalent circuits for the operation modes
are shown in Fig. 4. To simplify the analysis of the circuit operation, the following assumptions are made:
1) the leakage inductance of the transformer is neglected;
2) the line frequency is much lower than the switching frequency of the flyback converter so that the input voltage
Vin can be regarded as a constant during each switching
period;

MOON et al.: NEW CONTROL METHOD OF INTERLEAVED SINGLE-STAGE FLYBACK ACDC CONVERTER

Fig. 4.

4053

Equivalent circuits during one switching cycle. (a) Mode 1. (b) Mode 2. (c) Mode 3. (d) Mode 4. (e) Mode 5. (f) Mode 6.

3) the EMI filter capacitance Clter is greater than CIN , including the equivalent capacitance of the bridge diodes;
4) the magnetizing inductances Lm 1 and Lm 2 are identical;
5) the line voltage Vline is positive. Thus, diodes D1 and D4
are conducting;
6) the two switches, Q1 and Q2 , operate 180 out of phase.
Mode 1 (t0 t1 ): As can be seen in Fig. 4(a), Q1 is turned ON
and the energy is built into the magnetizing inductor Lm 1 , and
the energy stored in Lm 2 is transferred to the output. The drain
current ID S 1 of Q1 increases with the slope of Vin / Lm 1 , and
the diode current ID 6 decreases with the slope of N 2 Vo /Lm 2 .
This mode ends when ID 6 decreases to zero.
Mode 2 (t1 t2 ): When ID 6 equals zero, this mode begins. In
Fig. 4(b), the magnetizing inductor of T2 starts to resonate with
the output capacitor Coss2 of the switch Q2 . Because Q1 is still

ON, the diodes D1 and D4 are conducting. Thus, most of the

resonance currents flow through D1 , D4 , and the electromagnetic interference (EMI) filter. The resonance period TP 1 and
ID S 2 can be expressed as


(Clter +CIN ) Coss2
TP 1 = 2 Lm 2
2 Lm 2 Coss2
Clter +CIN +Coss2
(3)
ID S 2 = 

N Vo
Lm 2 /Coss2

sin

2
(t t1 ),
TP 1

t 1 t < t2

(4)

where Clter is greater than CIN and Coss2 .

Mode 3 (t2 t3 ): Mode 3 begins when Q1 is turned OFF. As
can be seen in Fig. 4(c), the diode current ID 5 decreases with

4054

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013

Fig. 5. Conventional and proposed control method. (a) PFM method at low line. (b) PWM method at low line. (c) Proposed method at low line. (d) PFM method
at high line. (e) PWM method at high line. (f) Proposed method at high line.

the slope of N 2 Vo /Lm 1 . Because Q1 is turned OFF, D1 and

D4 are no longer conducting. Thus, the resonance current flows
through CIN and the resonance period TP 2 can be expressed as


CIN Coss2
TP 2 = 2 Lm 2
2 Lm 2 Coss2 . (5)
CIN + Coss2

high ac line. The frequency variation between the low and high
lines is obtained as


2
V in
. h ig h
1
(6)
fPFM = flow
V in

If CIN is greater than Coss2 , the resonance period TP 2 is

almost the same as TP 1 .
In high ac line, the waveforms are similar except for the
switching period, the turn-ON time, and the duty cycle. The
switching period Tsw2 increases and the turn-ON time and the
duty cycle decreases to reduce the switching frequency variation
and the switching loss in high ac line.
Fig. 5 shows the conventional pulse frequency modulation
(PFM) method with constant duty cycle of 0.5, the constant frequency PWM method and the proposed method at low and high
ac lines. As shown in Fig. 5(a) and (d), the conventional PFM
method shows the disadvantage of a large frequency variation
between low and high ac lines. It causes severe switching loss at

where flow is the switching frequency at low line.

The proposed method is basically controlled by the switching
frequency in DCM operation. However, unlike the conventional
PFM method, as shown in Fig. 5(c) and (f), the turn-ON time
and the duty cycle of the proposed method is varied with the
switching frequency. If the switching frequency increases, the
turn-ON time and the duty cycle also increases, and vice versa.
The frequency variation of the proposed method between low
and high lines is obtained as


2
V in
Dm in
. h ig h

1
(7)
fprop osed = flow
V in
Dm ax

. low

. low

MOON et al.: NEW CONTROL METHOD OF INTERLEAVED SINGLE-STAGE FLYBACK ACDC CONVERTER

Fig. 6.

Simple block diagram of the proposed control method.

Fig. 7.

where Dm in is the duty cycle at full load with high ac line

condition, Dm ax is the duty cycle at full load with low ac line
condition and the value of Dm in over Dm ax is less than unity.
Thus, the proposed method reduces the switching frequency
variation when compared to the conventional PFM method.
As shown in Fig. 5(b) and (c), the rms current of the proposed
method is lower than that of the conventional PWM method in
low ac line so that the conduction loss of the proposed method is
reduced. In high ac line, the switching frequency of the proposed
method is lower than that of the conventional PWM method. As
a result, the switching loss of the proposed method is reduced.
Therefore, the proposed method can achieve high PF and
low THD by utilizing DCM operation, and it can achieve high
efficiency due to the variable switching frequency, turn-ON time
and duty cycle. However, the peak current at high ac line is
higher than that of the conventional PWM method as shown in
Fig. 5(e) and (f). Therefore, the transformer size may increase.
B. Proposed Control Scheme
Figs. 6 and 7 show a simple block diagram for the proposed
control method of the interleaved DCM flyback converter and
its key waveforms, respectively. In Fig. 6, the optotransistor
receives the output current information and draws current from
FB terminal. The current I1 is given by
I1 =

V1
Rf m in

V1 Vop
.
Rf m ax

4055

Key waveforms of the block diagram.

by aI1 and C2 is charged by the current source I3 . When the

capacitor voltage VC 2 increases to VR 1 , which is set by aI1
and R1 at t11 , the comparator COM4 outputs high signal. As a
result, SR2 is reset. Then, VG 1 becomes low and Q1 is turned
OFF. The turn-ON time of Q1 is obtained by
Ton = C2

VR 1
aI1 R1
= C2
.
I3
I3

(9)

After VG 1 becomes low at t11 , C1 is still charged by aI1 .

When VC 1 is equal to V2 at t22 , the comparator COM2 outputs
high signal. Thereby, SR1 is set. Then, M2 is turned ON again.
For the next one cycle, VG 1 remains low signal by DFF1, which
activates AND2 and deactivates AND1. Then, VG 2 goes to high
and turns ON Q2 in Fig. 4. Therefore, Q1 and Q2 are turned
ON by turns. The switching period TL of Q1 is twice the period
of the sawtooth signal VC 1 because of the interleaving control
method. The switching period is obtained by
TL = 2C1

V2 V3
.
aI1

(10)

From (9) and (10), Ton can be expressed as

(8)

The more the current I1 flows, the higher the switching frequency. At t00 , in Fig. 7, the switch M2 is turned ON. If the
current source I2 is much greater than the dependent current
source aI1 , I2 discharges the capacitor C1 very quickly. When
the capacitor voltage VC 1 becomes V3 , the comparator COM3
outputs high signal. Accordingly, SR1 is reset, SR2 is set and
the switch M3 is turned ON. As a result, M2 is turned OFF, the
D flipflop DFF1 outputs high signal, and the capacitor C2 is
discharged. Therefore, the signal of the gate driver1 VG 1 outputs
high signal and Q1 is turned ON in Fig. 4. Then, C1 is charged

Ton = 2C1 C2 R1

V2 V3
fL = m fL .
I3

(11)

Equation (11) shows that the turn-ON time is varied in proportion to the switching frequency. Therefore, the turn-ON time
and the switching frequency increase under heavy load in low
ac line condition and decrease under light load in high ac line
condition. The right side of Fig. 7 shows the waveforms under
heavy load condition. The turn-ON time and the switching frequency are increased. Table I is an example of the relationship
between the switching frequency and the turn-ON time.

4056

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013

TABLE I
EXAMPLE OF THE RELATIONSHIP OF FREQUENCY AND T o n

Load (%)
100
90
80
70
60
50
40
30
20
10

90Vac
Freq. (kHz)
Ton (s)
100
4.979
96.55
4.797
92.83
4.602
88.79
4.389
84.34
4.155
79.37
3.893
73.68
3.594
66.94
3.239
58.48
2.794
46.42
2.159

265Vac
Freq. (kHz)
Ton (s)
48.68
2.278
47.00
2.189
45.19
2.094
43.22
1.991
41.06
1.877
38.64
1.749
35.87
1.604
32.59
1.431
28.47
1.214
22.60
0.905

Fig. 9.

Drain current of the CRM flyback converter.

TABLE II
CONDUCTION LOSS COMPARISON AT LOW AC LINE

the DCM flyback configuration results in better PF and THD

when compared to the CRM flyback configuration.
Fig. 8.

Drain current of the DCM flyback converter.

B. Conduction Loss and Peak Current Comparison

III. ANALYSIS AND DESIGN CONSIDERATIONS

A. Input Current
Fig. 8 shows the drain current of the DCM flyback converter.
The input voltage Vin (t) can be expressed as

Vin (t) = 2Vac sin t

(12)
where Vac is the ac line voltage in rms. Then, the instantaneous
peak current Ipk (t) is obtained by

2Vac sin t
ton
(13)
Ipk (t) =
Lm
where Lm is the magnetizing inductance of the transformer.
From (13), the instantaneous average input current Iave (t) is
obtained by

2Vac sin t t2on

Iave (t) =

.
(14)
2Lm
Tsw
The instantaneous average current follows a sinusoidal envelope. On the other hand, as shown in Fig. 9, the instantaneous
average input current Iave (t) of the CRM flyback converter is
given by

2Vac sin t ton

1

Iave (t) =

(15)
2V
a c sin t
2Lm
1+
N Vo

where N Vo is the reflected output voltage. The instantaneous

average current has some distortion from a pure sinusoidal waveform due to the denominator of the right-side term in (15). Thus,

In low ac line and heavy load condition, the conduction loss

is dominant for the total power loss. To compare the proposed
method with the conventional constant frequency DCM method,
the following assumptions are made:
1) f1 = kfsw and f2 = fsw /k, where fsw is the switching
frequency of the conventional method, f1 and f2 are the
switching frequencies of the proposed method under full
load with low and high ac line conditions, respectively,
and k is a constant;
2) the turn-ON time ton is reverse proportion to the switching
period Tsw .
In Fig. 8, the rms current of the drain during one switching
period can be calculated as


2
 to n 
Vin
1
ton
Vin
ID S.rm s =
t dt =
ton
Tsw 0
Lm
Lm
3Tsw
(16)
where Vin is almost constant during one switching period. Then,
the instantaneous rms current can be expressed as


2Vac sin t
D
.
(17)
ton
ID S.rm s (t) =
Lm
3
From (17), the rms current during half of the ac line period is
obtained by


 T a c /2
2
D
Vac
2
.
ID S.rm s =
ID S.rm s (t) dt =
ton
Tac 0
Lm
3
(18)
Table II shows conduction loss comparison between the constant frequency DCM method and the proposed method under

MOON et al.: NEW CONTROL METHOD OF INTERLEAVED SINGLE-STAGE FLYBACK ACDC CONVERTER

Fig. 11.

Fig. 10.

4057

Switch network.

peak ac line voltage. Thus, the turns ratio is designed by

2V . laocw
Dm ax
N>

.
Vo
1 Dm ax

Peak current and conduction loss ratios with k.

full load with low ac line condition. It shows that

the conduction
loss of the proposed method is reduced by 1/ k.
As shown in Fig. 5(b) and (e), the peak current of the conventional method in high ac line is the same as that in a low ac line.
However, in the proposed method, the peak current in a high ac
line is given by

(19)
Ipk.high = k Ipk

(23)

In the proposed converter, the ID S.p eak in high ac line is

higher than that in low ac line. Thus, the minimum number of
turns for the primary side to avoid core saturation is given by
NPm in >

Lm ID S.p eak@high line

106
Bsat Ae

(24)

where Bsat is the saturation flux density in tesla and Ae is the

effective cross-sectional area in mm2 .
IV. SMALL-SIGNAL MODELING AND STABILITY

where Ipk.high is peak current in the high ac line of the proposed

method and Ipk is peak current in the conventional method. The
equation shows that the proposed method has the disadvantage
of higher peak current. The peak current and the conduction
loss ratios between the proposed and conventional methods are
shown in Fig. 10. The more k increases, the lower the conduction
loss and the higher the peak current become. Thus, k should be
designed with a trade off between the conduction loss and the
peak current.

v1 (t)t s (t) = vin (t)t s (t)

C. Transformer Design
In Fig. 8, the DCM single-stage flyback converter draws an
input power related to the drain peak current squared. Therefore,
the instantaneous input power can be expressed as
Pin (t) =

1
V 2 t2 fsw
2
Lm Ipk
(t)fsw = ac on
sin2 t. (20)
2
Lm

From (20), considering the efficiency and interleaving operation, the average input power over half of the ac line period
is obtained by
Pin =

V 2 t2 fsw
Pout
= ac on
.

Lm

(21)

Therefore, the magnetizing inductance for the worst case can

be designed as
Lm

Since the proposed converter operates in DCM, a small-signal

DCM model is needed to prove stability. In this section, a smallsignal model of the proposed converter is derived by the DCM
switch network [16], [17]. Because in the proposed control
method, two flyback converters operate in interleaving method,
small-signal models of the converters are the same. Considering
the upper side flyback converter of Fig. 2, the general two-switch
network is illustrated in Fig. 11. The averaged terminal voltages
and currents of the switch network in the DCM are obtained as

V 2a c t2on fsw
. low

Pout

(22)

where Vac.low is the low ac line voltage in rms.

The turns ratio N is required to prevent current distortion due
to undesired continuous conduction mode operation around the

v2 (t)t s (t) = vo (t)t s (t)

i1 (t)t s (t) =

d21 (t)ts (t)

v1 (t)t s (t)
2Lm 1

i2 (t)t s (t) =

2
d21 (t)ts (t) v1 (t)t s (t)

2Lm 1
v2 (t)t s (t)

(25)

where d1 (t) is duty cycle and ts (t) is switching period of Q1 . In

the proposed control method, since not only d1 (t), but also ts (t)
is time varying, the averaged current have four variables. The
averaged large-signal model of two-switch network in DCM
is illustrated in Fig. 12. The averaged transistor is modeled as
an effective resistor, and the averaged diode is modeled as a
power source, equal to consumption in the effective resistor.
However, the averaged switch network is nonlinear. Therefore,
the small-signal modeling of the converter needs perturbation
and linearization.
In the conventional pulsewidth pulse frequency modulation
control method [18][21] which changes both duty cycle and
frequency, there are two independent duty cycle and frequency
loops. Therefore, to obtain the small-signal switch network
equations, (25) should be expanded in a 4-D Taylor series. It

4058

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013

Fig. 13.
Fig. 12.

Small-signal model of the proposed converter.

Averaged large-signal model.

+ higher order nonlinear terms.

is difficult and complicated. On the other hand, in the proposed
control method, from (1), duty cycle can be expressed by
d1 (t) =

m
.
t2s (t)

r1 =

v1

+ j1 d +g1 v2
r1

i2

v2

= + j2 d +g2 v1 .
r2

i1 =

(27)

The parameters r1 , j1 , g1 , r2 , j2 , and g2 can be found by Taylor expansion about quiescent operating point as follows:
i1 (t)t s (t)

So, the first-order linear ac parameters r1 , j1 , g1 , r2 , j2 , and

g2 are given by

(26)

The duty cycle is not independent but inverse proportional

to switching period squared. As a result, the proposed control
method seems to have single loop, and the small-signal switch
network can be expressed in a 3-D Taylor series as the equation
of the conventional DCM flyback converter. So, the small-signal
switch network equations of i1 and i2 can be written by

d12 (t) m
=
v1 (t)t s (t)
2Lm 1


= f1 v1 (t)t s (t) , v2 (t)t s (t) , d1 (t)


f1 (v1 , V2 , D) 

v1
v 1 =V 1


f1 (V1 , v2 , D)

+ v2

v2
v 2 =V 2



f1 (V1 , V2 , d) 
+ d(t)

d
1

I1 + i1 (t) = f1 (V1 , V2 , D) + v1

d 1 =D

+ higher order nonlinear terms.

(28)
3

2
d 2 (t) m v1 (t)t s (t)
i2 (t)t s (t) = 1

2Lm 1
v2 (t)t s (t)


= f2 v1 (t)t s (t) , v2 (t)t s (t) , d1 (t)


f2 (v1 , V2 , D) 

I2 + i2 (t) = f2 (V1 , V2 , D) + v1

v1
v 1 =V 1


f2 (V1 , v2 , D)

+ v2

v2
v 2 =V 2



f2 (V1 , V2 , d) 
+ d(t)

d
1
d 1 =D

(29)

2Lm 1
3
m

D2

g1 = 0

3 D m V1
j1 =
.
4Lm 1

2Lm 1 V22
3
D 2 m V12
3
D 2 m V1
g2 =
Lm 1 V2

3 D m V12
j2 =
.
4Lm 1 V2

(30)

r2 =

(31)

As shown in Fig. 13, a small-signal model of the proposed

converter is obtained by replacing the MOSFET and diode with
the switch network model.
The control-to-output transfer function of the proposed converter has two poles and a right half-plane (RHP) zero. One pole
caused by Co appears at low frequency. But the other pole due
to the Lm 1 and a RHP zero occur at higher frequency about
switching frequency. Therefore, by low-frequency approximation, the proposed converter regards as single-pole system. In
low frequency, since Lm 1 seems to be short, a low-frequency approximation ac model is obtained as shown in Fig. 14. Therefore,
the control-to-output transfer function Gv d (s) and the line-tooutput transfer function Gv g (s) are obtained as


vo 
j2 (Ro r2 )
=
Gv d (s) = 

1 + sp
d v i n =0


vo 
g2 (Ro r2 )
Gv g (s) = 
=
1 + sp
vg 
d =0

p =

1
.
(Ro r2 )Co

(32)

In (32), the control-to-output transfer function of the proposed converter has one pole at low frequency like conventional
DCM flyback converter, so that the converter can have enough
phase margin. It makes easy to build the compensation network. Usually, proportional and integral controller is enough for

MOON et al.: NEW CONTROL METHOD OF INTERLEAVED SINGLE-STAGE FLYBACK ACDC CONVERTER

Fig. 14.

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Low-frequency approximation ac model.

Fig. 16.

LED configuration.

Fig. 17.

Waveforms with 265 Va c and full load condition.

Fig. 15. Bode plot of the control-to-output transfer function, when V in =

90 Va c , V o = 90 V, d1 = 0.4979, fs = 100 kHz, L m 1 = 215 H, C o =
1410 F, R o = 100 .
TABLE III
SPECIFICATIONS OF PROTOTYPE

Input voltage

90 ~ 265 Vac

Output voltage

9 ~ 90 Vdc

Output load current

900 mA

Output power

8.1 ~ 81 W

Switches (Q1, Q2)

FQA13N80

Diodes (D5, D6)

FFPF10U40S

LED unit

3 V, 300 mA

The proposed ISSF and 67 kHz ISSF

Magnetizing inductance (Lm1, Lm2)

215 H

Turns ratio (Np : Ns)

29 : 14

The 67 kHz single-stage flyback

Magnetizing inductance (Lm1)

180 H

Turns ratio (Np : Ns)

21 : 10

The two-stage boost-flyback

CRM boost inductance (L)

387 H

Flyback magnetizing inductance (Lm1)

1452 H

Turns ratio (Np : Ns)

49 : 25

Flyback switching frequency (fsw)

67 kHz

compensation. The Bode plot of Gv d (s) is illustrated in Fig. 15.

In practice, the second pole caused by Lm 1 and the RHP zero are
placed around several tens kilohertz. However, the bandwidth
of the controller of the proposed system should be narrow to

achieve high power factor. Therefore, the second pole and RHP
zero cannot affect the converter system.
V. EXPERIMENTAL RESULTS
A prototype of the proposed converter is implemented with
the specifications shown in Table III. For fair comparison,
the inductance and turns ratio should similar among the converters. However, unfortunately, the converters have different
topologies and control methods so that it is hard to design
similar value. Though the proposed and conventional converters
have different inductance and turns ratio, they are designed
optimally. The LED units are configured as shown in Fig. 16.
Since the number of LEDs in series varies according to LED
applications, the range of output voltage is wide. Minimum
output voltage is for low power applications such as the outdoor
pot light and maximum output voltage is set for high power
application like the flood light. To evaluate the validity of
the proposed converter, 67-kHz constant frequency singlestage DCM flyback converter, two-stage CRM boost-flyback

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 8, AUGUST 2013

Fig. 19. Efficiency, PF, and THD comparison at 90 Va c . (a) Efficiency.

(b) PF. (c) THD.

Fig. 18. Experimental waveforms of the proposed converter. (a) 90 Va c full

load condition. (b) 265 Va c full load condition. (c) 90 Va c 10% load condition.
(d) 265 Va c 10% load condition.

converter, and 67-kHz constant frequency ISSF converter are

also constructed and experimented on.
The interleaving operation of the proposed control method is
illustrated in Fig. 17 with 265 Vac and full load condition. Fig. 18
shows the experimental waveforms of the proposed converter.

Fig. 18(a) and (b) shows the waveforms of 90 Vac and 265 Vac
under the full load condition, respectively. The line current Iline
is a sinusoidal waveform and has same phase as the line voltage
Vline . The peak drain current ID S 1 .p eak at 265 Vac is higher than
that at 90 Vac due to lower switching frequency. This needs to
be considered when the transformer is designed. Fig. 18(c) and
(d) shows that the proposed converter still has the sinusoidal
waveform of Iline even if the load condition is very light.
Fig. 19 shows the efficiency, PF, and THD of the proposed
ISSF converter, constant frequency ISSF converter, single-stage
DCM flyback converter, and two-stage CRM boost-flyback converter at 90 Vac . Under the 100% load condition, the proposed
converter shows higher efficiency than the other converters because of the low rms current with high switching frequency. The
PF and THD are good in all of the converters due to the low

MOON et al.: NEW CONTROL METHOD OF INTERLEAVED SINGLE-STAGE FLYBACK ACDC CONVERTER

Fig. 21.

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LEDs current ripple.

Fig. 21 shows the current ripple of the LEDs. To reduce

the invisible flicker problem, the current ripple caused by the
line frequency should be low. The results show that the twostage configuration is the best solution for the invisible flicker
problem and that there is no current ripple cancelation even if
the interleaving control method is applied.
VI. CONCLUSION

Fig. 20. Efficiency, PF, and THD comparison at 265 Va c . (a) Efficiency.
(b) PF. (c) THD.

The PDPFM control method for an ISSF converter has been

proposed in this paper. The proposed control method increases
the switching frequency, the turn-ON time and the duty cycle
under heavy load with low ac line condition for low rms current
and it decreases under light load with high ac line condition for
low switching loss. Therefore, the proposed converter has high
efficiency for wide input voltage and output load ranges. Furthermore, the proposed converter is operated in DCM so that it
can achieve high PF and low THD for wide output power range.
The operational principles, design considerations, and smallsignal modeling have been presented. Because the proposed
converter has higher peak current than the conventional converters at high ac line, it should be considered when the transformer
is designed. To verify the validity of the proposed converter, an
81-W prototype was implemented and experimented on. The
results showed that the proposed converter has high efficiency,
high PF, and low THD. Therefore, the proposed converter is
considerably suitable for wide output range LED applications.
REFERENCES

ac line voltage. Usually in low ac line, the input current is less

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Fig. 20 shows the efficiency, PF, and THD at 265 Vac . In
Fig. 20(a), the proposed converter shows higher efficiency than
other converters under light load condition due to lower switching frequency. For the PF and THD, light load with high ac
line condition is the worst case due to the low drain current.
Therefore, the converter for wide output power range should
have high PF and low THD under that condition. Fig. 20(b)
and (c) show that the proposed converter has high PF and low
THD under light load with high ac line condition. Thus, the proposed converter is suitable for wide output power range LED
applications.

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SangCheol Moon (S10) was born in Jeju Island, Korea, in 1979. He received the B.S. degree in electrical
engineering from Ajou University, Suwon, Korea, in
2005, and the M.S. degree in electrical engineering
from Korea Advanced Institute of Science and Technology, Daejeon, Korea, in 2007, where he is currently working toward the Ph.D. degree in electrical
engineering.
In 2007, he joined Fairchild Semiconductor,
Bucheon, Korea, as a System and Application Engineer. His research interests include power electronics
including analysis, modeling, control method, power factor correction, LEDs,
and wireless power transfer circuit.

Gwan-Bon Koo was born in Seoul, Korea, in 1975.

He received the B.S., M.S., and Ph.D. degrees in electrical engineering from the Korea Advanced Institute
of Science and Technology, Daejeon, Korea, in 1997,
1999, and 2004, respectively.
He is currently a Principal Engineer with Fairchild
Korea Semiconductor, Ltd., Bucheon, Korea. His research interests include the areas of power electronics and control, including analysis, modeling, and
design of high-performance power converters, softswitching power converters, power factor correction,
and resonant converters. His research interests also include battery management
system, piezoelectric driver, and LED lighting system.

Gun-Woo Moon (S92M00) received the M.S.

and Ph.D. degrees in electrical engineering from the
Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1992 and 1996,
respectively.
He is currently a Professor in the Department of
Electrical Engineering, KAIST. His research interests include modeling, design, and control of power
converters, soft-switching power converters, resonant
inverters, distributed power systems, power factor
correction, electric drive systems, driver circuits of
plasma display panels, and flexible ac transmission systems.
Dr. Moon is a Member of the Korean Institute of Power Electronics, Korean
Institute of Electrical Engineers, Korea Institute of Telematics and Electronics,
Korea Institute of Illumination Electronics and Industrial Equipment, and Society for Information Display.