VERILOG PROBLEMS (CAD for VLSI)

Problem 1:
A0 B0

A1 B1

A2 B2

A3 B3

Full
Adder

Full
Adder

Full
Adder

Full
Adder

carry_out

carry_in

S0
(i)
(ii)

S1

S2

S3

Design a single-bit full adder module.

Design a four-bit adder using such four full adders (as designed above).

Problem 2:

req1
PRIORITY

gnt1

req2
ARBITER
rst

gnt2

clk
Design a priority arbiter (see the above figure) having following features:
(i)
Priority of req1 is higher than the priority of req2; i.e., whenever req1 is
high, gnt1 goes high in the next positive edge of the clk.
(ii)
Whenever req1 is low and req2 is high, gnt2 goes high in the next
positive edge of the clk.
(iii) When no requests are given, then both gnt1 and gnt2 remains low in next
clk.
(iv)
Make sure that your design should make gnt1 and gnt2 mutually exclusive.
(v)
Use rst signal to initialize your circuit and initially gnt1 and gnt2 must
remain low.
[ Hint: First build an FSM of the arbiter and then try to code that within a module ]
Now try to design a suitable test bench for this priority arbiter.

Problem 3:

bit-stream
clk

MODULO-3

remainder

CIRCUIT

Design a circuit which senses a bit-stream (one bit in every clock), and in every clock, it
produces the remainder by dividing the numerical value of the bit-stream (scanned up to
that clock) by three (i.e., bit-stream value % 3).
Also, initialize the remainder as 00 through initial block provided in Verilog.
[ Hint: For example, suppose the bit-stream is 100110.
Clock passed
bit-stream scanned
remainder-output
1
1
1 (as 12 = 110 & 1%3 = 1)
2
10
2 (as 102 = 210 & 2%3 = 2)
3
100
1 (as 1002 = 410 & 4%3 = 1)
4
1001
0 (as 10012 = 910 & 9%3 = 0)
.. etc etc..etc
Try to build the FSM and design the FSM module in Verilog ]

Problem 4:
Design a 256 8 bit RAM having asynchronous read and synchronous write capability.
When rw = 1, read operation is performed and when rw = 0, write operation is performed.
address

rw

256 8 bit
RAM

data

clk

Problem 5:
Design a 3-bit Grey Counter. The count starts with reset signal and the grey counter
counts when enable signal remains high and it stops counting whenever enable signal
goes low.
[ Hint: In a grey counter, the present and next binary value of the count differs only in
one bit position.
For example, the 2-bit grey counter counts as: 00 01 11 10 00 ]

Practice Examples (Try Youself):

1. Ring Counter, Johnson Counter.
2. GCD Calculator.
3. Bus Protocol consisting of Master, Slave and Arbiter Module.
a. First try to build individual FSM for master, slave, arbiter each and the
code them. Later, place three modules together in a top module.
b. Increase complexity of the design gradually by increasing the number
of master and slave modules.