HSUPA Resource Accessibility for NRT Traffic

HSUPA Active Cell throughput

HSUPA resource Retainability for NRT Traffic

R99 Setup Success Ratio from user perspective for NRT

Packet Session Setup Success Ratio (SSSR)

UL mlslot allocation blocking

Downlink multislot allocation blocking

100*
sum(ALLO_SUCCESS_EDCH_INT + ALLO_SUCCESS_EDCH_BGR)
/
sum(ALLO_SUCCESS_EDCH_INT +
ALLO_SUCCESS_EDCH_BGR +
EDCH_ALLO_CANC_NA_AS_BGR +
EDCH_ALLO_CANC_NA_AS_INT +
UL_DCH_SEL_MAX_HSUPA_USR_BGR +
UL_DCH_SEL_MAX_HSUPA_USR_INT +
UL_DCH_SEL_BTS_HW_INT +
UL_DCH_SEL_BTS_HW_BGR +
SETUP_FAIL_EDCH_BTS_BGR +
SETUP_FAIL_EDCH_BTS_INT +
SETUP_FAIL_EDCH_OTHER_BGR +
SETUP_FAIL_EDCH_OTHER_INT +
SETUP_FAIL_EDCH_TRANS_BGR +
SETUP_FAIL_EDCH_TRANS_INT +
SETUP_FAIL_EDCH_UE_BGR +
SETUP_FAIL_EDCH_UE_INT)
sum (edch_data_scell_ul + edch_data_nsc_s_edch_ul + edch_data_nsc_ns_edch_ul) * 8
----------------------------------------------------------------------------------sum (dur_hsupa_users_1_or_2 + dur_hsupa_users_3_or_4 + dur_hsupa_users_5_or_6 +
dur_hsupa_users_7_or_8 + dur_hsupa_users_9_or_10 + dur_hsupa_users_11_or_12 +
dur_hsupa_users_13_or_14 + dur_hsupa_users_15_or_16 + dur_hsupa_users_17_or_18 +
dur_hsupa_users_19_or_20 + dura_hsupa_users_21_to_24 + dura_hsupa_users_25_to_28 +
dura_hsupa_users_29_to_32 + dura_hsupa_users_33_to_36 + dura_hsupa_users_37_to_40 +
dura_hsupa_users_41_to_44 + dura_hsupa_users_45_to_48 + dura_hsupa_users_49_to_52 +
dura_hsupa_users_53_to_56 + dura_hsupa_users_57_to_60 + dura_hsupa_users_61_to_64 +
dura_hsupa_users_65_to_72)

100*
sum(REL_EDCH_NORM_INT +
REL_EDCH_NORM_BGR)
/
sum(REL_EDCH_NORM_INT +
REL_EDCH_NORM_BGR +
REL_EDCH_RL_FAIL_INT +
REL_EDCH_RL_FAIL_BGR +
REL_EDCH_OTHER_FAIL_INT +
REL_EDCH_OTHER_FAIL_BGR)
100*
sum(D_D_REQ_D_D_ALLO_INT + D_D_REQ_D_D_ALLO_BGR)
/
sum(PS_ATT_DCH_DCH_INT + PS_ATT_DCH_DCH_BGR)

100*
sum(HS_E_REQ_HS_E_ALLO_INT +
HS_E_REQ_HS_E_ALLO_BGR +
HS_E_REQ_HS_D_ALLO_INT +
HS_E_REQ_HS_D_ALLO_BGR +
HS_D_REQ_HS_D_ALLO_INT +
HS_D_REQ_HS_D_ALLO_BGR +
HS_E_REQ_D_D_ALLO_INT +
HS_E_REQ_D_D_ALLO_BGR +
HS_D_REQ_D_D_ALLO_INT +
HS_D_REQ_D_D_ALLO_BGR +
D_D_REQ_D_D_ALLO_INT +
D_D_REQ_D_D_ALLO_BGR+
HS_E_REQ_HS_E_ALLO_STRE +
HS_E_REQ_HS_D_ALLO_STRE +
HS_D_REQ_HS_D_ALLO_STRE +
HS_E_REQ_D_D_ALLO_STRE +
HS_D_REQ_D_D_ALLO_STRE +
D_D_REQ_D_D_ALLO_STRE)
/
sum(PS_ATT_HSDSCH_EDCH_INT +
PS_ATT_HSDSCH_EDCH_BGR +
PS_ATT_HSDSCH_DCH_INT +
PS_ATT_HSDSCH_DCH_BGR +
PS_ATT_DCH_DCH_INT +
PS_ATT_DCH_DCH_BGR +
PS_ATT_HSDSCH_EDCH_STRE +
PS_ATT_HSDSCH_DCH_STRE +
PS_ATT_DCH_DCH_STRE)
sum(NO_RADIO_RES_AVA_UL_TBF) 100 *
------------------------------------------------------------------------------sum(req_1_TSL_UL + req_2_TSL_UL +
req_3_TSL_UL + req_4_TSL_UL + req_5_TSL_UL +
req_6_TSL_UL + req_7_TSL_UL + req_8_TSL_UL)
Counters from table(s):
RBS_PS_PCU_{OBJ_AGG}_{TIME_AGG}
sum(NO_RADIO_RES_AVA_DL_TBF)
100 * ------------------------------------------------------------------------------sum(req_1_TSL_DL + req_2_TSL_DL + req_3_TSL_DL + req_4_TSL_DL
+ req_5_TSL_DL + req_6_TSL_DL + req_7_TSL_DL + req_8_TSL_DL
+ req_9_TSL_DL + req_10_TSL_DL + req_11_TSL_DL + req_12_TSL_DL)