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  • Self Bias Cascode

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    Shaik Abdul Rawoof
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    The document describes a self bias cascode transistor topology that consists of two transistors and a resistor. This structure is used for current mirroring. An input current is pumped into the "in" node, which biases the "src" and "cas" nodes. These biased nodes are then used for mirroring current. The design of the self bias cascode transistor refers to sizing the width-to-length ratios of transistors M1 and M2 and the resistor R. The design process starts by sizing M1 based on the fixed input current, so that M1 operates in saturation. This fixes the voltage at the "src" node, which then fixes the total voltage across M1 and M2.

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    Self Bias cascode

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    The document describes a self bias cascode transistor topology that consists of two transistors and a resistor. This structure is used for current mirroring. An input current is pumped into the "in" node, which biases the "src" and "cas" nodes. These biased nodes are then used for mirroring current. The design of the self bias cascode transistor refers to sizing the width-to-length ratios of transistors M1 and M2 and the resistor R. The design process starts by sizing M1 based on the fixed input current, so that M1 operates in saturation. This fixes the voltage at the "src" node, which then fixes the total voltage across M1 and M2.

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    © All Rights Reserved
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    14 views2 pages

    Self Bias Cascode

    Uploaded by

    Shaik Abdul Rawoof
    The document describes a self bias cascode transistor topology that consists of two transistors and a resistor. This structure is used for current mirroring. An input current is pumped into the "in" node, which biases the "src" and "cas" nodes. These biased nodes are then used for mirroring current. The design of the self bias cascode transistor refers to sizing the width-to-length ratios of transistors M1 and M2 and the resistor R. The design process starts by sizing M1 based on the fixed input current, so that M1 operates in saturation. This fixes the voltage at the "src" node, which then fixes the total voltage across M1 and M2.

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    © All Rights Reserved
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    Design of Self Bias Cascode Transistor

    Topology
    Abdul Rawoof Shaik
    shaik.abdul.rawoof@gmail.com
    s.rawoof@iitp.ac.in

    5th April,2014
    A self bias cascode transistor topology consists of 2 transistors and a
    resistor. The structure is as shown in the figure 1. This structure is used for
    current mirroring.
    in

    VDD

    M1

    src

    M2

    cas

    M2

    cas
    R

    M1

    src
    in
    Figure 1: Self Bias Cascode Structure

    An input current is pumped at in node, which biases src and cas nodes.
    These biased src and cas are used for mirroring. The design of self bias
    cascode transistor refers to the sizing of W/L for M1,M2 and R.
    Design steps starts with sizing of M1. A fixed input current flows from
    in node. Based on this fixed current we decide the size of M1 in such a way
    that M1 will be in saturation. Since Vsrc is fixed, this will fix Vds of M1 plus
    M2.
    Vds,M 1 + Vds,M 2 = Vsrc
    (1)

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