EE5320: Analog Integrated Circuit Design; Nagendra Krishnapura (nagendra@ee.iitm.ac.

in) 1

Assignment 2
Use the square law model with 𝜆 = 0 (𝑔 𝑑𝑠 = 0) for MOS transistors unless otherwise mentioned.

Rx
R
Ry s1

N branches
Vi +
− C Vo Ry s2

Ry sN

Figure 2.1: Problem 2.1.

2.1. The resistors and capacitors in a CMOS process vary by ±25% and ±15% respectively across process corners.
The RC filter in Fig. 2.1 is designed for a nominal bandwidth of 10 MHz.

(a) Determine the maximum and minimum bandwidths across process corners.
(b) The resistor is realized as a combination of a fixed resistor 𝑅 𝑥 and an array of 𝑁 equal resistors 𝑅 𝑦 that can
be switched in parallel. If the bandwidth has to be kept within 2.5% of the nominal bandwidth across all
corners, determine nominal values of 𝑅 𝑥 , 𝑅 𝑦 , and 𝑁 assuming a 10 pF capacitor (nominal value).

R
RP RN
Vi +
− C Vo

Figure 2.2: Problem 2.2.

2.2. Fig. 2.2 shows a 10 MHz bandwidth RC filter with a 10 pF capacitor. The resistor 𝑅 is realized as a series
combination of 𝑅 𝑃 and 𝑅 𝑁 which have a positive and negative temperature coefficients respectively in an
attempt to have the bandwidth invariant with temperature. The sheet resistances (at room temperature) and
temperature coefficients are as follows: 𝑅 𝑃 : 100 Ω/sq., +0.001/◦ C; 𝑅 𝑁 : 150 Ω/sq., −0.002/◦ C
The temperature dependence is modeled as 𝑅(𝑇) = 𝑅(𝑇0 )(1 + 𝛼(𝑇 − 𝑇0 )) where 𝑇0 is the room temperature and
𝛼 is the temperature coefficient. Determine the following such that the bandwidth is independent of temperature:

(a) Room temperature resistance values 𝑅 𝑃 (𝑇0 ) and 𝑅 𝑁 (𝑇0 ) and their Aspect ratios 𝐿 𝑃 /𝑊 𝑃 and 𝐿 𝑁 /𝑊 𝑁 .
(b) Maximum and minimum bandwidths in the −40 to 100◦ C range if only the positive temperature coefficient
resistor ( with the correct value at 27◦ C) is used.
2 EE5320: Analog Integrated Circuit Design; Nagendra Krishnapura (nagendra@ee.iitm.ac.in)

Vdd
M3 M4
Io

Vcm+vd/2 M1 M2

Vcm-vd/2
I1 + V
− out

Figure 2.3: Problem 2.3.

2.3. Fig. 2.3 shows a differential pair. All transistors are in the saturation region. Neglect 𝜆. Determine the following:

(a) Output current 𝐼𝑜 with 𝑣 𝑑 = 0 due to mismatch. The answer must be in terms of individual mismatch
values Δ𝑉𝑇 1−4 , (Δ𝛽/𝛽)1−4 , and transistor 𝑔𝑚 s.
(b) Standard deviation 𝜎𝐼 𝑜 of the output mismatch current in terms of 𝐴𝑉 𝑇 𝑁 , 𝐴 𝛽 𝑁 , 𝐴𝑉 𝑇 𝑃 , 𝐴 𝛽𝑃 , transistor
dimensions 𝑊1−4 , 𝐿 1−4 , and transistor 𝑔𝑚 s.
(c) Input voltage 𝑣 𝑑 that results in 𝐼𝑜 = 0. The answer must be in terms of individual mismatch values Δ𝑉𝑇 1−4 ,
(Δ𝛽/𝛽)1−4 , and transistor small signal parameters.
(d) Standard deviation of the above 𝑣 𝑑 in terms of 𝐴𝑉 𝑇 𝑁 , 𝐴 𝛽 𝑁 , 𝐴𝑉 𝑇 𝑃 , 𝐴 𝛽𝑃 , transistor dimensions 𝑊1−4 ,
𝐿 1−4 , and transistor 𝑔𝑚 s.

Vdd
Ii Io

M1 M2

Figure 2.4: Problem 2.4.

2.4. In Fig. 2.4, the switches are controlled by the signal 𝑠. The switches without the bubble are on and off for 𝑠 = 1
and 𝑠 = 0 respectively. The opposite is true for the switches with the bubble. The two transistors have the same
𝑊, 𝐿. They are in the saturation region. Neglect 𝜆. Sketch the circuit for 𝑠 = 1 and 𝑠 = 0. Determine the
following:

(a) Standard deviation of the current gain 𝐼𝑜 /𝐼𝑖 when 𝑠 is fixed at 1.

(b) Determine 𝑊 and 𝐿 if 𝐼𝑜 = 500µA, 𝑉GS − 𝑉𝑇 = 200 mV, and the standard deviation of the current gain is
1%. 𝐴𝑉 𝑇 = 5 mV µm, 𝐴 𝛽 = 1 % µm. Nominal values: 𝜇 𝑛 𝐶ox = 400 µA/V2 , 𝑉TN = 0.5 V.
(c) 𝑠 switches between 0 and 1 with a 50% duty cycle. Sketch 𝐼𝑜 (𝑡) for one cycle of 𝑠. Determine the time
average of 𝐼𝑜 (𝑡) over one period and its standard deviation.
EE5320: Analog Integrated Circuit Design; Nagendra Krishnapura (nagendra@ee.iitm.ac.in) 3

The answers must be in terms of 𝐴𝑉 𝑇 𝑁 , 𝐴 𝛽 𝑁 , transistor dimensions 𝑊, 𝐿, and transistor 𝑔𝑚 s.

Vtop
Iout

VGS

1 2 3 N-1 N
Figure 2.5: Problem 2.5.

2.5. Fig. 2.5 shows 𝑁 identical MOS transistors controlled by switches. Each transistor carries a nominal current 𝐼𝑜
and has an overdrive voltage 𝑉GS − 𝑉𝑇 . The switches are successively turned on. The output current is denoted
by 𝐼out [𝑛] when the switches 1 to 𝑛 are turned on. 0 ≤ 𝑛 ≤ 𝑁. Determine the following:

(a) Mean and standard deviation of 𝐼out [𝑛]/𝐼 𝑎𝑣𝑔 where 𝐼 𝑎𝑣𝑔 = 𝐼out [𝑁]/𝑁. The answer should be in terms of
𝐴𝑉 𝑇 , 𝐴 𝛽 , 𝑁, transistor dimensions 𝑊, 𝐿 and transistor 𝑔𝑚 . For what 𝑛 does it reach the maximum? What
is the maximum value?
(b) Mean and standard deviation of (𝐼out [𝑛 + 1] − 𝐼out [𝑛])/𝐼 𝑎𝑣𝑔 .
(c) Mean and standard deviation of (𝐼out [2𝑛 + 1] − 2𝐼out [𝑛])/𝐼 𝑎𝑣𝑔 . Briefly comment on this and the previous
result.

Hint: To keep the expressions compact, derive the expressions in terms of the total current error in the unit
source Δ𝐼𝑜 /𝐼𝑜 or its standard deviation. You can separately give the expression for 𝜎(Δ𝐼𝑜 /𝐼𝑜 ) in terms of the
transistor’s mismatch parameters.
Mismatch is relatively small. Use approximations such as (1 + 𝑥) (1 + 𝑦) ≈ 1 + 𝑥 + 𝑦 where applicable.