SR FLIP FLOP:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RS_FF is port (clk,rst,R,S:in std_logic;Q, Qbar:inout std_logic);
end RS_FF;
architecture arch_RS_FF of RS_FF is
begin
process(R,S,clk,rst)
begin
if(rst='1')then
Q<='Z';Qbar<='Z';
elsif(clk'event and clk='1')then
if(S='0' and R='0')then
Q<=Q;Qbar<=not Q;
elsif(S='0' and R='1')then
Q<='0';Qbar<='1';
elsif(S='1' and R='0')then
Q<='1';Qbar<='0';
elsif(S='1' and R='1')then
Q<='Z';Qbar<='Z';
end if;
end if;
end process;
end arch_RS_FF;

JK FLIP FLOP:
library ieee;
use ieee.std_logic_1164.all;
entity JK_FF is port (clk,rst,J,K:in std_logic;
Q, Qbar:inout std_logic);
end JK_FF;
architecture arch_JK_FF of JK_FF is
begin
process(J,K,clk,rst)
begin
if(rst='1')then
Q<='Z';Qbar<='Z';
elsif(clk'event and clk='1')then
if(J='0' and K='0')then
Q<=Q;Qbar<=not Q;
elsif(J='0' and K='1')then
Q<='0';Qbar<='1';
elsif(J='1' and K='0')then
Q<='1';Qbar<='0';elsif(J='1' and K='1')then
Q<=not Q;Qbar<=Q;
end if;end if;
end process;
end arch_JK_FF;

D FLIP FLOP:

Library ieee;
use ieee.std_logic_1164.all;
entity dff is port (clk,reset,d:in std_logic;q:out std_logic);
end dff;
architecture arch_dff of dff is
begin
process (d,clk,reset)
begin
if(reset='1') then
q<='0';
elsif(clk'event and clk='1') then
q<=d;
end if;end process;
end arch_dff ;

T FLIP FLOP:

Library ieee;
use ieee.std_logic_1164.all;
entity tff is port (clk,reset,t:in std_logic;q:out std_logic);
end tff;
architecture arch_tff of tff is
begin
process (t,clk,reset)
begin
if (reset='1') then
q<='0';
elsif (clk'event and clk='1') then
q<=not t;
end if;
end process;
end arch_tff;