Topics

Multipliers.

Modern VLSI Design 4e: Chapter 6

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2008 Wayne Wolf

Elementary school algorithm

0 1 1 0 multiplicand
x 1 0 0 1 multiplier
0110
+0000
00110
+0000
000110
+0110
0110110
Modern VLSI Design 4e: Chapter 6

partial product

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2008 Wayne Wolf

Word serial multiplier

Modern VLSI Design 4e: Chapter 6

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2008 Wayne Wolf

Combinational multiplier
Uses n adders, eliminates registers:

Modern VLSI Design 4e: Chapter 6

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2008 Wayne Wolf

Array multiplier
Array multiplier is an efficient layout of a
combinational multiplier.
Array multipliers may be pipelined to
decrease clock period at the expense of
latency.

Modern VLSI Design 4e: Chapter 6

Copyright

2008 Wayne Wolf

Array multiplier organization

0110
x multiplicand
1001
0110
+0000
multiplier
00110
+0000
000110
+0110
0110110
product
Modern VLSI Design 4e: Chapter 6

skew array
for rectangular
layout

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2008 Wayne Wolf

Unsigned array multiplier

x2y0

x1y2

x1y0

x1y1

x0y2

x0y0

x0y1

xny0

P(2n-1)

P(2n-2)

Modern VLSI Design 4e: Chapter 6

0
P0
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2008 Wayne Wolf

Baugh-Wooley multiplier
Algorithm for twos-complement
multiplication.
Adjusts partial products to maximize
regularity of multiplication array.
Moves partial products with negative signs
to the last steps; also adds negation of
partial products rather than subtracts.

Modern VLSI Design 4e: Chapter 6

Copyright

2008 Wayne Wolf

Booth multiplier
Encoding scheme to reduce number of
stages in multiplication.
Performs two bits of multiplication at once
requires half the stages.
Each stage is slightly more complex than
simple multiplier, but adder/subtracter is
almost as small/fast as adder.

Modern VLSI Design 4e: Chapter 6

Copyright

2008 Wayne Wolf

Booth encoding

Twos-complement form of multiplier:

y = -2nyn + 2n-1yn-2 + 2n-2yn-2 + ...

Rewrite using 2a = 2a+1 - 2a:

y = -2n(yn-1-yn) + 2n-1(yn-2 -yn-1) + 2n-2(yn-3 -yn-2) + ...

Consider first two terms: by looking at three

bits of y, we can determine whether to add x,
2x to partial product.

Modern VLSI Design 4e: Chapter 6

Copyright

2008 Wayne Wolf

Booth actions
yi yi-1 yi-2

increment

000
001
010
011
100
101
110
111

0
x
x
2x
-2x
-x
-x
0

Modern VLSI Design 4e: Chapter 6

Copyright

2008 Wayne Wolf

Booth example

x = 011001 (2510), y = 101110 (-1810).

y1y0y-1 = 100, P1 = P0 - (10 011001) =

11111001110.
y3y2y1= 111, P2 = P1 0 = 11111001110.

y5y4y3= 101, P3 = P2 - 0110010000 =

11000111110.

Modern VLSI Design 4e: Chapter 6

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2008 Wayne Wolf

Booth structure

Modern VLSI Design 4e: Chapter 6

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2008 Wayne Wolf

Wallace tree
Reduces depth of adder chain.
Built from carry-save adders:

three inputs a, b, c
produces two outputs y, z such that y + z = a + b +
c

Carry-save equations:
yi = parity(ai,bi,ci)
zi = majority(ai,bi,ci)

Modern VLSI Design 4e: Chapter 6

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2008 Wayne Wolf

Wallace tree structure

Modern VLSI Design 4e: Chapter 6

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2008 Wayne Wolf

Wallace tree operation

At each stage, i numbers are combined to
form ceil(2i/3) sums.
Final adder completes the summation.
Wiring is more complex.
Can build a Booth-encoded Wallace tree
multiplier.

Modern VLSI Design 4e: Chapter 6

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2008 Wayne Wolf

Serial-parallel multiplier
Used in serial-arithmetic operations.
Multiplicand can be held in place by
register.
Multiplier is shfited into array.

Modern VLSI Design 4e: Chapter 6

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2008 Wayne Wolf

Serial-parallel multiplier
structure

Modern VLSI Design 4e: Chapter 6

Copyright

2008 Wayne Wolf