Digital Logic: From

Transistors to Gates
Textbook Chapter 3

The Transistor

Transistor: building block of computers

Microprocessors contain tons of transistors
Intel Montecito (2005): 1.72 billion
Intel Pentium 4 (2000): 48 million
IBM PowerPC 750FX (2002): 38 million
IBM/Apple PowerPC G5 (2003): 58 million
Intel 4004 (1971): 2500

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01-2

The Transistor: Past and Present

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01-3

Moores Law
The number of active components per chip will double every 18 months.

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01-4

GPU Speed Compared to CPU

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01-5

Metal-Oxide-Semiconductor transistor

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01-6

How big is a transistor?

If a CPU die were as big as this whole

classroom
A transistor would be

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What is a transistor?

Logically, each transistor is used as a switch

Combined to implement logic functions
AND,

OR, NOT

Combined to build higher-level structures

Adder,

multiplexer, decoder, register,

Combined to build a processor

LC-3

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01-8

n-type MOS transistor

n-type MOS (nMOS)
when Gate has positive voltage,
short circuit between #1 and #2
(switch closed)
when Gate has zero voltage,
open circuit between #1 and #2
(switch open)

Gate = 1

Terminal #2 must be
connected to GND (0V).

CMPE12 Summer 2009

Gate = 0

01-9

p-type MOS transistor

p-type is complementary to n-type
when Gate has positive voltage,
open circuit between #1 and #2
(switch open)
when Gate has zero voltage,
short circuit between #1 and #2
(switch closed)

Gate = 1
Terminal #1 must be
connected to +2.9V in
this example.

CMPE12 Summer 2009

Gate = 0

01-10

Simple switch circuit

Switch open:
No

current through
circuit
Light is off
Vout is +2.9V

Switch closed:
Short

Switch-based circuits can

easily represent two states:
on/off, open/closed, voltage/no
voltage.
CMPE12 Summer 2009

circuit across
switch
Current flows
Light is on
Vout is 0V
01-11

Digital Values for Analog Signals

Use the switch behavior of MOS transistors to

implement logical functions: AND, OR, NOT
Digital symbols:
We assign a range of analog voltages to
each digital (logic) symbol
Assignment of voltage ranges depends on
electrical properties of transistors being used

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01-12

CMOS circuit

CMOS is Complementary Metal Oxide Semiconductor

Uses both n-type and p-type MOS transistors
p-type (pMOS)
Attached to + voltage
Pulls output voltage UP when input is zero
n-type (nMOS)
Attached to GND
Pulls output voltage DOWN when input is one

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Inverter (NOT gate)

In

Out

In

Out

0V

2.9 V

2.9 V

0V

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01-14

Truth Table

The most basic

representation of a logic
function
Lists the output for all
possible input
combinations
How many rows of the
truth table needed?

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Inputs

Outputs

AB

XY

2#inputs

01-15

Truth Table: Inverter

Inverted signals are

denoted with an overbar
Or with a prime symbol
A

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Input

Output

Y = A

01-16

Truth Table: AND Gate

The result of an AND

operation is 1 if and only
if all inputs are 1
Depict AND by the
multiplication symbol
AB
Or by lumping the signals
together
AB
We dont really build
these gates

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Inputs

Output

A B

Y=AB

01-17

NAND gate (NOT-AND)

Note: Parallel structure on top,

serial on bottom.
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A
0
0
1
1

B
0
1
0
1

C
1
1
1
0
01-18

AND gate
A
0
0
1
1

B
0
1
0
1

C
0
0
0
1

Add an inverter to
a NAND.

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Truth Table: OR Gate

The result of an OR
operation is 1 if and only
if any inputs are 1
Depict OR by the
addition symbol
A+B

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Inputs

Output

A B

Y=A+B

01-20

NOR Gate: NOT-OR

Note: Serial structure on top, parallel

on bottom.

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A
0
0
1
1

B
0
1
0
1

C
1
0
0
0
01-21

OR gate
A
0
0
1
1

B
0
1
0
1

C
0
1
1
1

Add an inverter to
a NOR gate.

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01-22

About the Little Circle

The little circle is what inverts

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01-23

Synthesis of AOI Gates

AOI means AND-OR-Invert

Truth table to a AOI gate (transistor-level)
Recall:
PMOS (with the bubbles) on top
NMOS (no bubbles) on bottom
Series structure makes AND
Parallel structure makes OR

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01-27

Synthesis of AOI Gates

Method 1: sum of products

Start with ones
Build pull-up branch first
Method 2: sum of products
Start with zeros
Build pull-down branch first
Use inverters to complement inputs and output
Which method?
Depends on the truth table
More ones: method 1
More zeros: method 2

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01-28

Synthesis of AOI Gates

Method 1: Sum of products for Y

Cover the ones
Build pull-up branch first using inverted inputs
Derive pull-down branch as the dual of pull-up
branch
VDD
Y=
C

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VSS
01-29

Synthesis of AOI Gates

Method 2: Sum of products for Y

Cover the zeros
Build pull-down branch first, using asserted inputs
Derive pull-up branch as a dual of the pull-down
branch
VDD
Y=
C

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VSS
01-30

Recommended exercises
Combinational circuits
Ex 3.5, 3.6, 3.7, 3.8, 3.9
Ex 3.11, 3.12, 3.18
Ex 3.20, 3.22, 3.23, 3.24 with TA/Tut
Ex 3.30, 3.31, 3.35
Ex 3.44

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01-31