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Ic Applications Lab Manual: Iii Btech, Ece-Ist Semester
Ic Applications Lab Manual: Iii Btech, Ece-Ist Semester
[TYPE
FOR
By
KUMAR GOUD.K
Asst.Professor
[Type text]
IC APPLICATIONS LAB
III ECE (I SEM)
LIST OF EXPERIMENTS (As per JNTU Syllabus)
PART-1
1.
2.
3.
4.
5.
6.
7.
8.
9.
PART-2
1.
2.
3.
4.
5.
4-bit Comparator(74LS85)
6.
7.
8.
ECE
IC APPLICATIONS LAB
DONTS
DOS
1.
2.
3.
4.
ECE
Name of the
Component/Equipment
IC 741
Resistors
Resistors
Resistor
Regulated Power Supply
Function Generator
Cathode Ray Oscilloscope
Multimeter
Bread Board
Probes & Connecting wires
Specifications
Refer Appendix
Quantity
A
3.3 K,2.2K
1K
10k
(0 30V),1A
(0.1 1MHz),20Vp-p
(0 20MHz)
3 digit display
1
2
4
2
1
1
1
1
THEORY:
Adder: A two input summing amplifier may be constructed using the inverting mode. The adder can be
obtained by using either non-inverting mode or differential amplifier. Here the inverting mode is used. So
the inputs are applied through resistors to the inverting terminal and non-inverting terminal is grounded.
This is called virtual ground, i.e. the voltage at that terminal is zero. The gain of this summing amplifier is
1; any scale factor can be used for the inputs by selecting proper external resistors.
Subtractor: A basic differential amplifier can be used as a subtractor. If all resistors are equal in value then
output voltage can be derived by using superposition principle. To find V01 due to V1 alone make V2=0.Then
the circuit becomes a non inverting amplifier having input voltage V1/2 at the non inverting input terminal
and output becomes
V01=V1/2[1+R/R]
=V1
Similarly the output
V02 = -V2
Thus the output voltage V0 due to both the inputs can be written as
V0= V01+V02
= V1-V2
Comparator: It is a circuit which compares a signal voltage applied at one input terminal of op-amp with a
known reference voltage at the other input. Non inverting comparator circuit is shown in figure. A fixed
reference voltage is applied to (-) input and time varying signal Vi is applied to (+) input.
The output voltage is at
Vsat for Vi<Vref.
And Vo goes to
+Vsat for Vi>Vref.
The output waveform for a sin input signal applied to (+) input as shown.
RVR INSTITUTE OF ENGINEERING & TECHNOLOGY (IBRAHIM PATAN, HYDERABAD)
ECE
CIRCUIT DIAGRAMS:
Fig1.1: Adder
Fig1.2: Subtractor
Fig1.3: Comparator
RVR INSTITUTE OF ENGINEERING & TECHNOLOGY (IBRAHIM PATAN, HYDERABAD)
ECE
PROCEDURE:
Adder:
1. Connect the circuit as per the diagram shown in fig 1.1.
2. Apply the supply voltages of +15V to pin7 and -15V to pin4 of IC 741 respectively.
3. Apply the DC inputs V1 and V2.
4. Vary the input voltages and note down the corresponding outputs at pin 6 of the IC 741
5. Notice that the output is equal to the sum of the two inputs.
Subtractor:
i/p2(v)
V0(v) practical
V0(v) Theoretical
ECE
Subtractor:
i/p1 (v)
i/p2(v)
V0(v) Practical
V0(v) Theoretical
PRECAUTIONS:
1. Check the connections before giving the power supply.
2. Readings should be taken carefully.
RESULT:
ECE
Specifications
Quantity
Refer Appendix A
0.1f, 0.01f
1
Each one
Each one
2
1
1
1
159, 1.5k
(0 30V),1A
(0.1 1MHz), 20V p-p
(0 20MHz)
THEORY:
Integrator: In an integrator circuit, the output voltage is the integration of the input voltage. The output
voltage of an integrator is given by
Vo = -1/R1Cf Vidt.
At low frequencies the gain becomes infinite, so the capacitor is fully charged and behaves like an open
circuit. The gain of an integrator at low frequency can be limited by connecting a resistor in shunt with
capacitor.
Differentiator: In the differentiator circuit the output voltage is the differentiation of the input voltage. The
output voltage of a differentiator is given by Vo = - RfC1 dVin/df .The input impedance of this circuit
decreases with increase in frequency, thereby making the circuit sensitive to high frequency noise. At high
frequencies circuit may become unstable. For pin configuration and specifications of op amp (IC 741).
ECE
CIRCUIT DIAGRAMS:
Fig2.1: Integrator
Fig2.2: Differentiator
CALCULATIONS (Theoretical):
Integrator:
Choose T = 2RfCf
Where T= Time period of the input signal
Assume Cf and find Rf
Select Rf = 10R1
t/2
Vi (p-p) dt
0
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10
Differentiator
Select given frequency fa = 1/ (2 Rf C1), Assume C1 and find Rf
Select fb = 10 fa = 1/2 R1C1 and find R1
From R1C1 = Rf Cf, find Cf
PROCEDUER:
Integrator
1. Connect the circuit as per the diagram shown
2. Apply a square wave/sine input of 4V (p-p) of 1 KHz
3. Observe the o/p at pin 6.
4. Draw input and output waveforms as shown.
5. Observe that theoretical & practical values are equal.
Differentiator
1. Connect the circuit as per the diagram shown
2. Apply a square wave/sine input of 4V (p-p) of 1 KHz
3. Observe the output at pin 6
4. Draw the input and output waveforms as shown
5 Observe that theoretical & practical values are equal.
WAVE FORMS:
Integrator
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11
Differentiator
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12
OBSERVATION TABLES:
Integrator
Input Square wave
Amplitude(Vp-p)
(V)
Time period
(ms)
Output - Triangular
Amplitude(Vp-p)
(V)
Time period
(ms)
Time period
(ms)
Output - cosine
Amplitude(Vp-p)
(V)
Time period
(ms)
Differentiator
Input Square wave
Amplitude(Vp-p)
(V)
Time period
(ms)
Output - Triangular
Amplitude(Vp-p)
(V)
Time period
(ms)
Time period
(ms)
Output - cosine
Amplitude(Vp-p)
(V)
Time period
(ms)
MODEL CALCULATIONS:
Integrator:
For T= 1 msec
fa = 1/T = 1 KHz
fa = 1 KHz = 1/(2RfCf)
Assuming Cf= 0.1f, Rf is found from Rf=1/(2 fa Cf)
Rf =1.59 K
Rf = 10 R1
R1= 159
RVR INSTITUTE OF ENGINEERING & TECHNOLOGY (IBRAHIM PATAN, HYDERABAD)
ECE
13
Differentiator:
For T = 1 msec
f= 1/T = 1 KHz
fa = 1 KHz = 1/ (2RfC1)
Assuming C1= 0.1f, Rf is found from Rf=1/(2faC1)
Rf=1.59 K
Fb = 10 fa = 1/2 R1C1
for C1= 0.1f;
R1 =159
PRECAUTIONS:
1. Check the connections before giving the power supply.
2. Readings should be taken carefully.
RESULT:
1. What is an op-amp?
2. What are the applications of op-amp?
3. What is meant by integrator and differentiator?
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14
Name of the
Component/Equipment
Specifications
Quantity
IC 741
Refer Appendix A
Resistors
10k
Resistors
3.3k
Capacitors
0.01f
(0 20MHz)
(0 30V),1A
Function Generator
(1Hz 1MHz)
Bread Board
THEORY:
a) LPF:
A LPF allows frequencies from 0 to higher cut of frequency fH. At fH the gain is 0.707 Amax, and after fH
gain decreases at a constant rate with an increase in frequency. The gain decreases 40dB each time the
frequency is increased by 10. Hence the rate at which the gain rolls off after fH is 40dB/decade or 12 dB/
octave, where octave signifies a two fold increase in frequency. The frequency f=fH is called the cut off
frequency because the gain of the filter at this frequency is down by 3 dB from 0 Hz. Other equivalent terms
for cut-off frequency are -3dB frequency, break frequency, or corner frequency.
b) HPF:
The frequency at which the magnitude of the gain is 0.707 times the maximum value of gain is called low
cut off frequency. Obviously, all frequencies higher than fL are pass band frequencies with the highest
frequency determined by the closed loop band width all of the op-amp.
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15
CIRCUIT DIAGRAMS:
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16
PROCEDURE:
1. Connections are made as shown in the circuit diagram
2. Apply sine wave i/p signal of peak amplitude 5 volts.
3.
Check the gain of non-inverting amplifier by keeping the frequency of the input signal in the pass
band of the filter. Note down the output voltage Vo max.
4. Keeping the input signal amplitude constant, vary the frequency until the output voltage reduces to
0.707 Vo max, the corresponding frequency is the cut-off frequency (fc) of the filter.
To find the Roll-off factor:1. For LPF: - Keeping the input signal amplitude constant, adjust the input frequency at 10fc gives the
Roll-off factor.
2. For HPF: - Keeping the input signal amplitude constant, adjust the input frequency at 0.1fc note down
the output signal amplitude. The difference in the gain of the filter at fc and 0.1 fc gives the Roll-off
factor.
OBSERVATION TABLES:
Vi(p-p) =
Volts (Constant)
Gain magnitude
(Vo/Vi)
Gain magnitude in
db =20log(Vo/Vi)
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17
Vi (p-p) =
Volts (Constant)
Gain magnitude
(Vo/Vi)
Gain magnitude in
db =20log(Vo/Vi)
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18
PRECAUTIONS:
1. Check the connections before giving the power supply.
2. Readings should be taken carefully.
3. VCC and VEE must be given to the corresponding pins.
RESULT:
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19
AIM: To Design a RC Phase Shift & Wein Bridge Oscillators of output frequency 200 Hz.
Specification
Quantity
Resistor
Resistor
Resistor
Variable Resistor
Capacitor
Capacitor
741 IC
Bread Board
Dual Channel Power Supply
Cathode Ray Oscilloscope
Connecting wires &Probes
3.3 K
33K
12K
1.2M,50K
0.1f
0.05 f
Refer Appendix -A
3
2
1
Each one
3
2
1
1
1
1
(0-30V)
(0 20MHz)
CIRCUIT DIAGRAMS:
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20
ii. The gain Av at the above frequency must be at least 29 i.e Rf/R1=29
iii. fo= 200Hz
Let C = 0.1f , Then
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21
The gain required for sustained oscillations is given by Av= 3. i.e., Rf=2R1
Let C = 0.05uf
Now let R1=12K,
Then fo = 1/ (2
) => R=3.3K
then Rf =2R1=24K
PROCEDURE:
1. Construct the circuits as shown in the circuit diagrams.
2. Adjust the potentiometer Rf that an output wave form is obtained.
3. Calculate the output wave form frequency and peak to peak voltage
4. Compare the theoretical and practical values of the output waveform frequency
OBSERVATIONS:
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22
RESULT:
VIVA-VOICE:
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23
COMPONENTS REQUIRED:
Name of the
Component/Equipment
Specifications
Quantity
IC 555
Refer Appendix B
Resistor
10k
Capacitors
0.1f,0.01f
Each one
Bread Board
(0 20MHz)
(0 30V),1A
THEORY:
A Monostable Multivibrator, often called a one-shot Multivibrator, is a pulse-generating circuit in which the
duration of the pulse is determined by the RC network connected externally to the 555 timer. In a stable or
stand by mode the output of the circuit is approximately Zero or at logic-low level. When an external trigger
pulse is obtained, the output is forced to go high (VCC). The time the output remains high is determined
by the external RC network connected to the timer. At the end of the timing interval, the output
automatically reverts back to its logic-low stable state. The output stays low until the trigger pulse is again
applied. Then the cycle repeats. The Monostable circuit has only one stable state (output low), hence the
name monostable. Normally the output of the Monostable Multivibrator is low. When the power supply
VCC is connected, the external timing capacitor C charges towards VCC with a time constant (RA+RB)
C. During this time, pin 3 is high (VCC) as Reset R=0, Set S=1 and this combination makes Q =0 which
has unclamped the timing capacitor C. For pin configuration and specifications, see Appendix-B
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24
CIRCUIT DIAGRAMS:
Model calculations:
If C=0.1 F , RA = 10k then tp = 1.1 mSec
Trigger Voltage = 4V
PROCEDURE:
1. Connect the circuit as shown in the circuit diagram as shown in Fig.
2. Apply Negative triggering pulses at pin 2 of frequency 1 KHz as shown in Fig
3. Observe the output waveform and capacitor voltage as shown and measure the pulse duration.
4. Theoretically calculate the pulse duration as tp=1.1. RaC
5. Compare it with experimental values.
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25
MODEL WAVEFORMS:
Fig 5.3 (a): Trigger signal (b): Output Voltage (c): Capacitor Voltage
Sample Readings:
Trigger
0 to 5V range
1)1V,0.09msec
Output wave
0 to 5V range
4.6V, 0.5msec
Capacitor output
0 to 3.33 V range
3V, 0.88 msec
PRECAUTIONS
Check the connections before giving the power supply.
Readings should be taken carefully.
RESULT:
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26
Name of the
Component/Equipment
Specifications
Quantity
IC 741
Refer Appendix A
IC 555
Refer Appendix B
Resistor
100
Resistor
56 K
Resistor
100 K
Capacitors
0.01f
Multimeter
3 digit display
Bread Board
(0 20MHz)
(0 30V),1A
THEORY:
Schmitt trigger circuit using IC 741
The circuit shows an inverting comparator with positive feed back. This circuit converts arbitrary wave
forms to a square wave or pulse. The circuit is known as the Schmitt trigger (or) squaring circuit. The input
voltage Vin changes the state of the output Vo every time it exceeds certain voltage levels called the upper
threshold voltage Vut and lower threshold voltage Vlt. When Vo = - Vsat, the voltage across R1 is referred to
as lower threshold voltage, Vlt. When Vo=+Vsat, the voltage across R1 is referred to as upper threshold
voltage Vut. The comparator with positive feed back is said to exhibit hysteresis, a dead band condition.
Schmitt trigger circuit using IC555
Apart from the timing functions, the two comparators of the 555 timer can be used independently for other
applications. One example is a Schmitt Trigger shown here. The two comparator inputs (pin 2 & 6) are tied
together and biased at 1/2 Vcc through a voltage divider R1 and R2.Since the threshold comparator will trip
at 2/3 Vcc and the trigger comparator will trip at 1/3Vcc,the bias provided by the resistors R1 & R2 are
centered within the comparators trip limits. By modifying the input time constant on the circuit, reducing the
value of input capacitor (C1) 0.001 uf so that the input pulse get differentiated, the arrangement can also
be used either as a bistable device or to invert pulse wave forms. In the later case, the fast time combination
of C1 with R1 & R2 causes only the edges of the input pulse or rectangular waveform to be passed. These
pulses set and reset the flip-flop and a high level inverted output is the result.
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27
CIRCUIT DIAGRAMS:
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28
Design:
Vutp = [R1/ (R1+R2)] (+Vsat)
Vltp = [R1/ (R1+R2)] (-Vsat)
Vhy = Vutp Vltp
= [R1/ (R1+R2)] [+Vsat (-Vsat)]
PROCEDURE:
1. Connect the circuit as shown in figures.
2. Apply an arbitrary waveform (sine/triangular) of peak voltage greater than UTP to the input of a
Schmitt trigger.
3. Observe the output at pin6 of the IC 741 and at pin3 for IC 555 Schmitt trigger circuits by
varying the input and note down the readings as shown in Table 1 and Table 2
4. Find the upper and lower threshold voltages (Vutp, VLtp) from the output wave form.
WAVE FORMS:
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29
OBSERVATIONS:
Table 1:
IC 741
Parameter
IC 555
Voltage( Vp-p),V
Time period(ms)
Table 2:
Parameter
IC 741
IC 555
Vutp
Vltp
PRECAUTIONS:
RESULTS:
ECE
30
COMPONENTS REQUIRED:
Name of the
Component/Equipment
Specifications
Quantity
IC 723
IC 7805
IC7809
IC7912
Resistor
Refer Appendix C
Each one
3.3K,4.7K,100
Each one
Variable Resistors
1K, 5.6K
Each one
(0 30V),1A
Bread Board
THEORY:
A voltage regulator is a circuit that supplies a constant voltage regardless of changes in load current and
input voltage variations. Using IC 723, we can design both low voltage and high voltage regulators with
adjustable voltages. For a low voltage regulator, the output VO can be varied in the range of voltages VO
<Vref, where as for high voltage regulator, it is VO > Vref. The voltage Vref is generally about 7.5V.Although
voltage regulators can be designed using Op-amps, it is quicker and easier to use IC voltage Regulators.IC
723 is a general purpose regulator and is a 14-pin IC with internal short circuit current limiting, thermal
shutdown, current/voltage boosting etc. Furthermore it is an adjustable voltage regulator which can be varied
over both positive and negative voltage ranges. By simply varying the connections made externally, we can
operate the IC in the required mode of operation. Typical performance parameters are line and load
regulations which determine the precise characteristics of a regulator. The pin configuration and
specifications are shown in the Appendix-c.
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31
CIRCUIT DIAGRAM:
PROCEDURE:
a) Line Regulation:
1. Connect the circuit as shown in fig 1.
2. Obtain R1 and R2 for Vo=5V
3. By varying Vn from 2 to 10V, measure the output voltage Vo.
4. Draw the graph between Vn and Vo as shown in model graph (a)
5. Repeat the above steps for Vo=3V
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32
Sample Readings
a) Line Regulation:
Vo set to 5V
Vi (v)
Vo set to 3V
Vi (v)
Vo(v)
Vo(v)
b) Load Regulation:
Vo set to 5V
IL (mA)
Vo set to 3V
Vo(v)
IL (mA)
Vo(v)
MODEL GRAPHS:
a) Line Regulation
b) Load Regulation
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33
PRECAUTIONS:
1. Check the connections before giving the power supply.
2. Readings should be taken carefully.
RESULTS:
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34
LOGIC SYMBOL:
ECE
35
LOGIC DIAGRAM:
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36
TRUTH TABLE:
THEORY:
The D flip-flop is also known as the Data flip-flop or the Delay flip-flop. It is used to either store
the data or introduce a delay. If a 0 is given at Din, then S is 0 and R will be 1. This resets the flip-flop.
If a 1 is given at Din, and then S is 1 and R 0. This sets the flip-flop. Thus we find that D out is always
equal to Din. Hence this flip-flop can be used to store a binary digit. So it is known as the Data flip-flop. The
D flip-flop can also be clocked similar to the RS flip-flop. In the clocked D flip-flop D out will be made
equal to D in only when the clock arrives. Thus the data bit is sent to the output after a delay. Therefore, the
D flip-flop is also known as the Delay flip-flop.
PROCEDURE:
1. Connections are made as per the circuit diagram.
2. Connect the preset terminal to logic 1 and then clear the circuit by connecting the clear terminal to
1
logic 0. Observe Q and Q .
3. Connect the preset terminal to logic 0 and clear terminal to logic 1.
1
4. Observe Q and Q .
5. Now apply +ve edge triggered circuit clock and change the values of D to 0 and 1.
1
6. Now verify the values of Q and Q .
PRECAUTIONS:
1.
2.
VIVA QUESTIONS:
2.
3.
4.
5.
6.
7.
8.
9.
What is D-FF?
Define a latch?
Define a FF?
What is the difference b/w latch & FF?
In flip-flop how many stable states are there?
What is edge triggering
What is level triggering
I/P of D-F/F =1, then what is the O/P value Q=
ECE
37
2. DECADE COUNTER-7490
AIM: To study the operation of decade counter using IC7490.
APPARATUS:
1.
2.
3.
4.
IC 7490
Bread board IC trainer kit.
Connecting wires.
Patch cords.
PIN DIAGRAM:
LOGIC DIGRAM:
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38
LOGIC SYMBOL:
OBSERVATIONS:
QD
QC
QB
QA
Decimal
Equivalent
output
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
9
THEORY:
The decade counter (mod-10 counter) is used most often. In order to count from 0 through 9, a
counter with 3 flip-flops is not sufficient. With 4 flip-flops one can count from 0 to15 (16 states). Out of
these 16 states, we should skip any 6 states. In the decade counter, when the output is 1010(for the 10th
clock pulse), all the flip-flops should be reset. Thus the outputs Q3 and Q1 are given directly to the inputs of
the AND gate and the outputs Q2 and Q0 are given through inverters. Therefore, for the 10th clock pulse,
the counter output would be 1010 for a moment. This sends the output of the AND gate to HIGH clearing all
the flip-flops. Thus a decade counter has been developed.
PROCEDURE:
1.
2.
3.
ECE
4.
5.
6.
7.
8.
9.
10.
11.
39
PRECAUTIONS:
1.
2.
3.
VIVA QUESTIONS:
1.
2.
3.
4.
5.
6.
7.
What is a counter?
what are the asynchronous inputs
To restrict the count value of a counter, if takes the help of inputs.
To restrict the count value of a counter, if takes the help of inputs.
Define mod up counter.
Define mod down counter.
Difference b/w mod-up counter and mod-down counter.
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40
APPARATUS:
1.
2.
3.
4.
Bread board.
IC 7495.
Patch cords.
Connecting wires.
PIN DIAGRAM:
LOGIC SYMBOL:
ECE
41
THEORY:
A shift register is an n-bit register with a provision for shifting its stored data by one bit position
at each tick of the clock. The serial input, SERIN, specifies a new bit to be shifted into one end at each clock
tick. This bit appears at the serial output, SEROUT, after n clock ticks, and is lost one tick later. Thus, an
n-bit serial-in, serial-out shift register can be used to delay a signal by n clock ticks. A serial-in, parallel-out
shift register has outputs for all of its stored bits, making them available to other circuits. Such a shift
register can be used to perform serial-to-parallel conversion. Conversely, it is possible to build a parallel-in,
serial-out shift register. At each clock tick the register either loads new data from inputs 1D-ND or it shifts
its current contents, depending on the value of the LOAD/SHIFT control input. The device uses a 2-input
multiplexer on each flip-flops D input to select between the two cases. A parallel-in, serial-out shift register
can be used to perform parallel-to-serial conversion. By providing outputs for all of the stored bits in a
parallel-in shift register, we obtain the parallel-in, parallel-out shift register. Such a device is general enough
to be used in any of the applications of the previous shift registers.
PROCEDURE:
1.
2.
3.
4.
5.
6.
Mount the IC 7495 on logic trainer and make the required connections.
Connect pins-2, 3, 4, 5 of the IC to logic switches SW1, SW2, SW3 and SW4 for applying low
and high logic levels at this input.
The serial input is given to pin-1 and mode control to pin-6.
Pins-8 and 9 are shorted and connected to clock pulse.
Connect Vcc=+5v to pin-14.
Pin-7 is grounded.
CLEARING FUNCTION:
1.
2.
3.
4.
After the register has been cleared, any 4-bit serial number can be loaded into the register.
Set mode control switch to low.
Set the serial input to high.
Apply a clock pulse which will shift the serial input 1 into the register, in this case QA is 1.
Return serial input switch SW3 to low and apply three clock pulses. The register will show an
output of 00001.We can load any 4-bit number into the register in this way.
3.
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42
PRECAUTIONS:
1.
2.
VIVA QUESTIONS:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
What is a register?
What is a shift register?
What are the operations performed by a shift register?
Applications of SISO shift register.
Applications of PISO shift register.
Applications of SIPO shift register.
Applications of PIPO shift register.
What is the IC package?
What is a universal shift register?
What are the operations performed by a universal shift register?
Applications of SISO universal shift register.
Applications of PISO universal shift register.
Applications of SIPO universal shift register.
Applications of PIPO universal shift register.
What is the IC package?
Difference b/w shift register and universal shift register.
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43
4. 3 - 8 DECODER- 74138
AIM: To verify the operation of 3 to 8 line decoder using IC 74138.
APPARATUS:
1.
2.
3.
4.
IC 74138.
Bread board trainer kit
Patch cords
Connecting wires.
PIN DIAGRAM:
LOGIC SYMBOL:
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44
LOGIC DIAGRAM:
TRUTH TABLE:
THEORY:
n
Decoder is the combinational circuit which contains n input lines to 2 output lines. The decoder
is used for converting the binary code into the octal code. The IC74138 is the 3*8 decoder which contains
three inputs and eight outputs and also three enables out of them two are active low and one is active high.
Decoders are used in the circuit where required to get more outputs than that of the inputs which also used in
the chip designing process for reducing the IC chip area.
PROCEDURE:
1.
2.
3.
4.
5.
6.
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45
7. When E3 is low all the outputs are high irrespective of E11 and E21 and high
8. If E11 and E21 are low and E31 is high, the inputs are low, the outputs O01 will be low with all the
other outputs are low.
9. Similarly by changing the inputs we get (one) 1 output as low and all other outputs as high.
10. When all inputs are high O71 will be low and all other will be high
PRECAUTIONS:
1. All the pins should be identified properly.
2. Supply voltage should not exceed +5v.
3. Avoid loose connections on the bread board.
VIVA QUESTIONS:
1.
2.
3.
4.
5.
6.
7.
8.
What is decoder?
What is a encoder?
For a 2- I/P decoder how many O/Ps are produced
A decoder with n input produces max. of __ no.of minterms.
The general representation of an encoder is
Draw the 2 to 4 line decoder with only nor gates.
Difference b/w de multiplexer and decoder
The general representation of an encoder is for economical realization, decoder is used to realize a
function which contain ( Less no. of dont cares)
9. A 16 to 64 decoder can be obtained by cascading of
10. Can more than one decoder O/P be activated at one time?
RESULT: The working of the 3 to 8 decoder is verified using IC 74138
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LOGIC SYMBOL:
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LOGIC DIAGRAM:
FUNCTION TABLE;
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THEORY:
Comparing two binary words for equality is a commonly used operation in computer systems and
device interfaces. A circuit that compares two binary words and indicates whether they are equal is called a
comparator. Some comparators interpret their input words as signed or unsigned numbers and also indicate
an arithmetic relationship (greater or less than) between the words. These devices are often called magnitude
comparators. A 1-bit Comparator is designed using Ex-OR and Ex-NOR gates. The outputs of 4 XOR gates
are ORed to create a 4-bit comparator. The IC 7485 is 4-bit magnitude comparator. With respect to the 8
inputs 3 inputs are cascaded inputs. After the 8 input operations are performed further the outputs are based
on the cascaded inputs.
PROCEDURE:
1. Connect the circuit as per Pin diagram.
2. Give the inputs A [A3, A2, A1, A0] and B [B3,B2,B1,B0] according to function table.
3. Give the cascaded inputs IA>B, IA=B, IA<B and verify the outputs.
4. Tabulate the inputs and outputs according to function table.
PRECAUTIONS:
1. All the pins should be identified properly.
2. Supply voltage should not exceed +5v.
3. Avoid loose connections on the bread board.
VIVA QUESTIONS:
1. What is Magnitude Comparator?
2. To form a 12 bit comparator how many 4-bit comparators are connected in cascaded form.
3. The IC 7485 is a package and is a ____ comparator.
4. How many cascaded input are there for a 4-bit comparator.
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6. 8 x 1 MULTIPLEXER-74150
AIM: To verify the operation of 8*1 multiplexer using IC 74150.
APPARATUS:
1.
2.
3.
4.
IC74150.
Bread board IC trainer kit.
Patch cords.
Connecting wires.
PIN DIAGRAM:
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LOGIC SYMBOL:
TRUTH TABLE
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THEORY:
A multiplexer is a digital switch- it connects data from one of n sources to its output. An 8*1 is
multiplexer consists of 3 input lines as select lines and 8 input lines and 1 output line. A multiplexer is a
unidirectional device which follows the data from input lines to output lines. Multiplexers are obviously
useful device in any application in which data must be multiple source to destination. A common application
in computers is the mux between the processors registers and its ALU.
PROCEDURE:
1. Connections are made as per logic diagram.
2. Connect the inputs D0 to D7 .
3. Give data select inputs and verify outputs according to truth table.
PRECAUTIONS:
1. All the pins should be identified properly.
2. Supply voltage should not exceed +5v.
3. Avoid loose connections on the bread board.
VIVA QUESTIONS:
1. Mux is an implementation of
2. Multiplexer is represented by
3. De multiplexer is represented by
RESULT: 8*1 multiplexer is verified using IC74150.
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IC74189.
Bread board IC trainer kit.
Patch cords.
Connecting wires.
PIN DIAGRAM:
LOGIC SYMBOL:
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LOGIC DIAGRAM:
FUNCTION TABLE:
MEMORY ENABLE
WRITE ENABLE
OPERATION
THEORY:
The 74LS189 is a high speed 64-bit Ram organized as a 16- word by 4-bit array. Address inputs are buffered
to minimize loading and are fully decoded on-chip. The outputs are 3-state and are in the high impedance
state whenever the Memory Enable (ME) input is HIGH. The outputs are active only in the Read mode and
the output data is the complement of the stored data. Here A0-A3 are the Address Inputs, D1-D4 are Data
inputs, O1-O4 are Inverted Data Outputs.
PROCEDURE:
This experiment has 3 stages Clearing the memory, data entry (Write operation) and data
verification (Read operation).
1) The memory Enable pin is used to select 1- of-n ICs i.e. like a Chip Select signal.
For simply city, the memory enable pin is permanently held low.
2) The address lines are given through an up /down counter with preset capability.
3) The set address switch is held high to allow the user choose any location in the RAM, using the address
bits.
4) The address and data bits are used to set an address and enter the data.
5) The Read/Write switch is used to write data on to the RAM.
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ADDRESS
0h - 0000
1h - 0001
2h - 0010
3h - 0011
4h - 0100
5h - 0101
6h - 0110
7h - 0111
8h - 1000
9h - 1001
10h - 1010
11h - 1011
12h - 1100
13h - 1101
14h - 1110
15h - 1111
DATA
Ah - 1010
Bh - 1011
4h - 0100
7h - 0111
Ch - 1100
1h - 0001
Fh - 1111
5h - 0101
8h - 1000
3h - 0011
Eh - 1110
9h - 1001
Dh - 1101
0h - 0000
2h - 0010
6h - 0110
1. Assume that the following data has to be written on to the RAM. The address and data are given in the
hexadecimal format.
2. Position the Stack/Queue switch in the Queue position.
3. Position the Read/Write switch in the Write position to enable the entry of data in to the RAM.
4. Position the Set Address switch in the 1 position to allow random access of memory.
5. Set the desired address (any address at random) using the address bit switches.
6. Set the desired data (refer table for the data to be entered in each location) using the data bit Switches.
7. Observe that the data is indicated by the LEDs (D3 toD0). This is because the data is written on to the
RAM.
8. Also observe that the data is indicated by the data outputs is the compliment of the data input (refer truth
table condition ME =L and WE=L).
RVR INSTITUTE OF ENGINEERING & TECHNOLOGY (IBRAHIM PATAN, HYDERABAD)
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9. After each data entry, make a note of the location where data is entered. This is to make sure that we are
not re entering data in the same location.
10. Repeat steps 4 and 5 until data has been entered in all the addresses listed in the above table
11. Position the Read/Write switch in the Read position, to disable data entry.
12. This completes data entry.
READ OPERATION: 1.
2.
3.
4.
5.
QUESTIONS:
1. What is the RAM?
2. Give the applications of the RAM?
3. What is the difference between RAM &ROM?
4. What is the difference between static RAM &dynamic RAM?
5. Which can be used as 1-bit memory?
6. What are the different types of the ROM?
7. What are the parameters of the RAM?
8. What is refreshing of memory? And where it is required?
9. What are sequential access memories?
10. What are charge-coupled devices?
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APPENDIX A
IC 741
Pin Configuration:
Specifications:
1. Voltage gain A = typically 2, 00,000
2. I/P resistance RL = , practically 2M
3. O/P resistance R1 =0, practically 75
4. Bandwidth = Hz. It can be operated at any frequency
5. Common mode rejection ratio = (Ability of op amp to reject noise voltage)
6. Slew rate + V/sec(Rate of change of O/P voltage)
7. When V1 = V2, VD=0
8. Input offset voltage (Rs 10K) max 6 mv
9. Input offset current = max 200nA
10. Input bias current: 500nA
11. Input capacitance: type value 1.4PF
12. Offset voltage adjustment range: 15mV
13. Input voltage range: 13V
14. Supply voltage rejection ratio : 150 r/V
15. Output voltage swing: + 13V and 13V for RL > 2K
RVR INSTITUTE OF ENGINEERING & TECHNOLOGY (IBRAHIM PATAN, HYDERABAD)
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APPENDIX B
IC 555
Pin Configuration:
Specifications:
1. Operating temperature
2. Supply voltage
: +5V to +18V
3. Timing
: Sec to Hours
4. Sink current
: 200mA
5. Temperature stability
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APPENDIX C
IC723
Pin Configuration:
Specifications of 723:
Power dissipation
: 1W
Input Voltage
: 9.5 to 40V
Output Voltage
: 2 to 37V
Output Current
Load regulation
: 0.6% Vo
Line regulation
: 0.5% Vo
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REFERENCES
1. Anand Kumar, Pulse and Digital Circuits, PHI
2. David A. Bell, Solid State Pulse circuits, PHI
3. D.Roy Choudhury and Shail B.Jain, Linear Integrated Circuits, 2nd edition, New Age International.
4. James M. Fiore, Operational Amplifiers and Linear Integrated Circuits: Theory and Application, WEST.
5. J.Milliman and H.Taub, Pulse and digital circuits, McGraw-Hill.
6. Ramakant A. Gayakwad, Operational and Linear Integrated Circuits, 4th edition, PHI.
7. Roy Mancini, OPAMPs for Everyone, 2nd edition, Newnes.
8. S. Franco, Design with Operational Amplifiers and Analog Integrated Circuits, 3rd edition, TMH.
9. William D. Stanley, Operational Amplifiers with Linear Integrated Circuits, 4th edition, Pearson.
10. www.analog.com.
11. www.datasheetarchive.com
12. www.ti.com
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