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Dien Tu So Co Ban
Dien Tu So Co Ban
om
.v
ch
.c
Ti liu bao gm cc kin thc c bn v mch cng logic, c s i s logic, mch logic t
hp, cc trig, mch logic tun t, cc mch pht xung v to dng xung, cc b nh thng dng.
c bit l trong ti liu ny c b xung thm phn logic lp trnh v ngn ng m t phn cng
VHDL. y l ngn ng ph bin hin nay dng to m hnh cho cc h thng k thut s. Tt
c gm 9 chng. Trc v sau mi chng u c phn gii thiu v phn tm tt gip ngi
hc d nm bt kin thc hn. Cc cu hi n tp ngi hc kim tra mc nm kin thc
sau khi hc mi chng. Trn c s cc kin thc cn bn, ti liu c gng tip cn cc vn
hin i, ng thi lin h vi thc t k thut.
te
.4
Chng 7: B nh bn dn.
Chng 8: Logic lp trnh.
Chng 9 : Ngn ng m t phn cng VHDL.
Do thi gian c hn nn ti liu ny khng trnh khi thiu st, rt mong ngi c gp .
Cc kin xin gi v Khoa K thut in t 1- Hc vin Cng ngh Bu chnh vin thng.
Xin trn trng cm n.
Chng 1: H m
CHNG 1: H M
GII THIU
om
.v
ch
.c
te
NI DUNG
.4
Nguyn tc chung ca biu din l dng mt s hu hn cc k hiu ghp vi nhau theo qui
c v v tr. Cc k hiu ny thng c gi l ch s. Do , ngi ta cn gi h m l h
thng s. S k hiu c dng l c s ca h k hiu l r. Gi tr biu din ca cc ch khc
nhau c phn bit thng qua trng s ca h. Trng s ca mt h m bt k s bng ri, vi i
l mt s nguyn dng hoc m.
Tn h m
S k hiu
C s (r)
H nh phn (Binary)
0, 1
H bt phn (Octal)
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7, 8, 9
10
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F
16
Bng 1.1
Ngi ta cng c th gi h m theo c s ca chng. V d: H nh phn = H c s 2, H
thp phn = H c s 10...
2
Chng 1: H m
Di y, ta s trnh by tm tt mt s h m thng dng.
1.1.1 H thp phn
Cc k hiu ca h nh nu bng 1.1. Khi ghp cc k hiu vi nhau ta s c mt
biu din. V d: 1265,34 l biu din s trong h thp phn:
= di 10i
n 1
om
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n : s ch s phn nguyn,
ch
m : s ch s phn phn s.
.c
te
.4
= a n 1 r n 1 + ... + a1 r1 + a 0 r 0 + a 1 r 1 + ... + a m r m
w
w
= a i ri
n 1
Trong mt s trng hp, ta phi thm ch s trnh nhm ln gia biu din ca cc h.
V d: 3610 , 368 , 3616 .
1.1.2 H nh phn
1.1.2.1. T chc h nh phn
H nh phn (Binary number system) cn gi l h c s hai, gm ch hai k hiu 0 v 1, c
s ca h l 2, trng s ca h l 2n. Cch m trong h nh phn cng tng t nh h thp phn.
Khi u t gi tr 0, sau ta cng lin tip thm 1 vo kt qu m ln trc. Nguyn tc cng
nh phn l : 0 + 0 = 0, 1 + 0 = 1, 1 + 1 = 10 (102 = 210).
3
Chng 1: H m
Trong h nh phn, mi ch s ch ly 2 gi tr hoc 0 hoc 1 v c gi tt l "bit". Nh
vy, bit l s nh phn 1 ch s. S bit to thnh di biu din ca mt s nh phn. Mt s nh
phn c di 8 bit c gi 1 byte. S nh phn hai byte gi l mt t (word). Bit tn cng bn
phi gi l bit b nht (LSB Least Significant Bit) v bit tn cng bn tri gi l bit ln nht
(MSB - Most Significant Bit).
Biu din nh phn dng tng qut :
N 2 = b n 1b n 2 ....b1b0 .b 1b 2 ....b m
0.
s nh phn phn s
22
21
20
21
22
om
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N2
= b n 1 2n 1 + ... + b1 21 + b0 20 + b 1 21 + ... + b m 2 m
.c
= b i 2i
ch
n 1
te
b. Php tr
.4
Khi tr nhiu bit nh phn, nu cn thit ta mn bit k tip c trng s cao hn. Ln tr k
tip li phi tr thm 1.
c. Php nhn
Qui tc nhn hai bit nh phn nh sau:
0x0=0 , 0x1=0 ,1x0=0 ,1x1=1
Php nhn hai s nh phn cng c thc hin ging nh trong h thp phn.
Ch : Php nhn c th thay bng php dch v cng lin tip.
d. Php chia
Php chia nh phn cng tng t nh php chia hai s thp phn.
u im chnh ca h nh phn l ch c hai k hiu nn rt d th hin bng cc thit b c,
in. Cc my vi tnh v cc h thng s u da trn c s hot ng nh phn (2 trng thi). Do
4
Chng 1: H m
, h nh phn c xem l ngn ng ca cc mch logic, cc thit b tnh ton hin i - ngn
ng my.
Nhc im ca h l biu din di, mt nhiu thi gian vit, c.
1.1.3 H bt phn v thp lc phn
1.1.3.1 H bt phn
om
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N8
= O n 1 8n 1 + ... + O0 80 + O 1 81 + ... + O m 8 m
m
= Oi 8i
.c
n 1
Lu rng, h thp phn cng m tng t v c gii rng hn h bt phn, nhng khng
ch
te
a. Php cng
.4
Php cng trong h bt phn c thc hin tng t nh trong h thp phn. Tuy nhin,
khi kt qu ca vic cng hai hoc nhiu ch s cng trng s ln hn hoc bng 8 phi nh ln
ch s c trng s ln hn k tip.
b. Php tr
Cc php tnh trong h bt phn t c s dng. Do , php nhn v php chia dnh li
nh mt bi tp cho ngi hc.
1.1.3.2 H thp lc phn
1.T chc ca h
H thp lc phn (hay h Hexadecimal, h c s 16). H gm 16 k hiu l 0, 1, 2, 3, 4, 5,
6, 7, 8, 9, A, B, C, D, E, F.
Trong , A = 1010 , B = 1110 , C = 1210 , D = 1310 , E = 1410 , F = 1510 .
Chng 1: H m
N16
= Hi 16i
n 1
Khi tng hai ch s ln hn 15, ta ly tng chia cho 16. S d c vit xung ch s tng
v s thng c nh ln ch s k tip. Nu cc ch s l A, B, C, D, E, F th trc ht, ta phi
i chng v gi tr thp phn tng ng ri mi cng.
om
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b. Php tr
.c
Mun thc hin php nhn trong h 16 ta phi i cc s trong mi tha s v thp phn,
nhn hai s vi nhau. Sau , i kt qu v h 16.
ch
te
thc hin vic i mt s thp phn y sang cc h khc ta phi chia ra hai phn:
phn nguyn v phn s.
.4
i vi phn nguyn: ta chia lin tip phn nguyn ca s thp phn cho c s ca h cn
chuyn n, s d sau mi ln chia vit o ngc trt t l kt qu cn tm. Php chia dng li
khi kt qu ln chia cui cng bng 0.
57/2
28
28/2
14
14/2
7/2
3/2
1/2
Bc
LSB
MSB
Chng 1: H m
Phn nguyn ta va thc hin v d a), do ch cn i phn phn s 0,375.
Bc
Nhn
Kt qu
Phn nguyn
0,375 x 2
0.75
0,75 x 2
1.5
0,5 x 2
1.0
0,0 x 2
57,37510 = 111001.01102
om
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Kt qu : 0,37510 = 0,01102
= a n 1 r n 1 + .... + a 0 r 0 + a 1 r 1 + .... + a m r m
N10
.c
ch
.4
te
a. i s 110111,01112 sang s h c s 8
Chng 1: H m
1.3 S NH PHN C DU
1.3.1 Biu din s nh phn c du
C ba phng php th hin s nh phn c du sau y.
1. S dng mt bit du. Trong phng php ny ta dng mt bit ph, ng trc cc bit tr
s biu din du, 0 ch du dng (+), 1 ch du m (-).
2. S dng php b 1. Gi nguyn bit du v ly b 1 cc bit tr s (b 1 bng o ca cc
bit cn c ly b).
3. S dng php b 2
om
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L phng php ph bin nht. S dng th hin bng s nh phn khng b (bit du bng
0), cn s m c biu din qua b 2 (bit du bng 1). B 2 bng b 1 cng 1.
C th biu din s m theo phng php b 2 xen k: bt u t bit LSB, dch v bn tri,
gi nguyn cc bit cho n gp bit 1 u tin v ly b cc bit cn li. Bit du gi nguyn.
1.3.2 Cc php cng v tr s nh phn c du
.c
ch
te
.4
b. Php tr. Nu lu rng, - (-) = + th trnh t thc hin php tr trong trng hp ny
cng ging php cng.
2. Cng v tr cc s theo biu din b 1
a. Cng
Hai s m: biu din chng dng b 1 v cng nh cng nh phn, k c bit du. Bit trn
cng vo kt qu. Ch , kt qu c vit di dng b 1.
Hai s khc du v s dng ln hn: cng s dng vi b 1 ca s m. Bit trn c
cng vo kt qu.
Hai s khc du v s m ln hn: cng s dng vi b 1 ca s m. Kt qu khng c bit
trn v dng b 1.
b. Tr
thc hin php tr, ta ly b 1 ca s tr, sau thc hin cc bc nh php cng.
8
Chng 1: H m
3. Cng v tr nh phn theo biu din b 2
a. Cng
Hai s dng: cng nh cng nh phn thng thng. Kt qu l dng.
Hai s m: ly b 2 c hai s hng v cng, kt qu dng b 2.
Hai s khc du v s dng ln hn: ly s dng cng vi b 2 ca s m. Kt qu bao
gm c bit du, bit trn b i.
Hai s khc du v s m ln hn: s dng c cng vi b 2 ca s m, kt qu dng
b 2 ca s dng tng ng. Bit du l 1.
b. Php tr
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1.4. DU PHY NG
1.4.1 Biu din theo du phy ng
ch
.c
1/ 2 M 1
te
.4
X = 2E x ( M x ) v Y = 2
Tch: Z = X.Y = 2
( M y ) th:
E x +E y
Thng: W = X / Y = 2
( M x .M y ) = 2E
E x E y
Mz
( M x / M y ) = 2E
Mw
TM TT
Trong chng ny chng ta gii thiu v mt s h m thng c s dng trong h
thng s: h nh phn, h bt phn, h thp lc phn. V phng php chuyn i gia cc h m
.
Ngoi ra cn gii thiu cc php tnh s hc trong cc h .
Chng 1: H m
CU HI N TP
1. nh ngha th no l bit, byte?
2. i s nh phn sau sang dng bt phn: 0101 1111 0100 1110
a. 57514
b. 57515
c. 57516
3. Thc hin php tnh hai s thp lc phn sau: 132,4416 + 215,0216.
om
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a. 347,46
b. 357,46
c. 347,56
d. 357,67
.c
ch
.4
d. 0000 0010
te
b. 0000 0100
c. 0000 0011
a. 1000 1110
b. 1000 1011
c. 1000 1100
d. 1000 1110
d. 57517
om
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.c
.4
te
ch
CM trng
thi Ngt:
A= 0
CM trng
thi ng:
A=1
NI DUNG
2.1 I S BOOLE
2.1.1. Cc nh l c bn:
Tn gi
Dng tch
Dng tng
ng nht
X.1 = X
X+0=X
Phn t 0, 1
X.0 = 0
X+1=1
X.X = 0
Bt bin
X.X = X
Hp th
X + X.Y = X
Ph nh p
X=X
nh l
DeMorgan
om
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STT
X + X =1
X+X=X
.c
X.(X + Y) = X
ch
te
.4
12
m0
m1
m2
m3
m4
m5
m6
m7
om
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N = 22
.c
ch
te
.4
+ Dng hi: Mi tha s l hng tng hay maxtex, thng c k hiu bng ch "Mi".
Nu trong tt c mi hng tch hay hng tng c mt cc bin, th dng tng cc tch hay tch
cc tng tng ng c gi l dng chun. Dng chun l duy nht.
Tng qut, hm logic n bin c th biu din ch bng mt dng tng cc tch:
f ( X n 1,..., X 0 ) =
2n 1
a i mi
i =0
13
f ( X n 1,..., X 0 ) =
2n 1
( a i + mi )
i =0
f = AB + AC + BC
p dng nh l, A + A = 1 , X + XY = X ta c:
f = AB + AC + BC ( A + A )
= AB + ABC + AC + ABC
.c
= AB + AC
om
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te
ch
Vy nu trong tng cc tch, xut hin mt bin v o ca bin trong hai s hng khc
nhau, cc tha s cn li trong hai s hng to thnh tha s ca mt s hng th ba th s
hng th ba l tha v c th b i.
.4
2. Thay mi nhm bng mt hng tch mi, trong gi li cc bin ging nhau theo dng
v ct.
3. Cng cc hng tch mi li, ta c hm ti gin.
V d: Hy dng bng Cc n gin c hm :
f ( A, B, C ) = (1, 2, 3, 4, 5 )
Li gii:
BC
00
01
11
10
f1 = B
Hnh 2-2
14
f 2 = AC
f = f1 + f 2 = B + AC
Nu gp cc c gi tr 0 li theo hai nhm, ta thu c biu thc hm b f :
f = AB + BC
om
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1. Lp bng lit k cc hng tch di dng nh phn theo tng nhm vi s bit 1 ging
nhau v xp chng theo s bit 1 tng dn.
.c
ch
te
.4
Bng a
Bng b
Nh phn
Rt gn ln u.
Rt gn ln th 2.
sp xp
ABCD
ABCD
ABCD
10
1010
1 0 1 - # (10,11)
11--
(12,13,14,15)
12
1100
1 - 1 0 # (10,14)
1-1-
(10,11,14,15)
11
1011
1 1 0 - # (12,13)
13
1101
1 1 - 0 # (12,14)
14
1110
1 - 1 1 # (11,15)
15
1111
1 1 - 1 # (13,15)
Hng tch
1 1 1 - # (14,15)
Bng 2.3
Bc 2: Thc hin nhm cc hng tch (bng 2.3b).
15
10
A BCD
11
11-1-1-
12
13
14
15
x
Bng 2.4
T bng 2-4, ta nhn thy rng 4 ct c duy nht mt du "x" ng vi hai hng 11-- v 1-1-.
Do , biu thc ti gin l :
om
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f ( A, B, C, D ) = AB + AC
.c
ch
te
f = f ( A, B ) = A.B
.4
f ( A, B, C, D,...) = A.B.C.D...
A
B
C
D
E
&
A
B
C
D
E
&
16
om
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t1
t2
t0
t3
t4
t5
te
.4
ch
.c
t6
t7
t8
Li vo A
Li ra f
0
Li vo B
0
t9
t10
V d : Dng cng AND to "ca" thi gian. Trong ng dng ny, trn hai li vo ca
cng AND c a ti 2 chui tn hiu s X, Y c tn s khc nhau. Gi s tn s ca X ln hn
tn s ca Y. Trn u ra cng AND ch tn ti tn hiu X, gin on theo tng chu k ca Y. Nh
vy, chui s Y ch gi vai tr ng, ngt cng AND v thng c gi l tn hiu "ca". Hot
ng ca mch c m t bng hnh 2-5.
17
1s
1s
om
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f ( A, B ) = A + B
f ( A, B, C, D...) = A + B + C + D + ...
.c
A
B
te
A
B
C
D
E
ch
.4
A
B
C
D
E
a) Theo gi tr logic
b) Theo mc in th
18
1 0
t2
t1
t0
t3
t4
t5
t6
t7
1
t8
t9
A
f
t10
om
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.c
ch
te
.4
A = 0 th A = 1 ,
nu A = 1 th A = 0
Hnh 2-9
a) Theo gi tr logic
b) Theo mc logic
19
0 0
1 1 1
0
t
V
0
H
t
0
0 0
1 1 1
b) Logic dng vi mc m.
om
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.c
Khi ghp ba loi cng logic c bn nht s thu c cc mch logic t n gin n phc
tp. y ta ch xt mt vi mch ghp n gin nhng rt thng dng.
ch
te
Ghp ni tip mt cng AND vi mt cng NOT ta c cng NAND (Hnh 2-11).
A
AB
f = AB
.4
f =
AB
f = ABCD...
K hiu cng NAND (hnh 2-12a,b) v bng trng thi (bng 2-8).
A
B
C
A
B
C
D
&
&
om
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f = A + B hay f = A + B + C + ...
A+B
A+B
.c
A
B
ch
te
.4
Hot ng ca cng NOR c gii thch bng bng trng thi nh ch bng 2.9a,b.
A
AB
B
A
f = AB + AB
AB
Hnh 2-15. S ca cng XOR 2 li vo
f = AB + AB
f = AB
om
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.c
=1
.4
0
te
ch
Hot ng cng XOR nhiu li vo cng tng t nh cng 2 li vo, ngha l nu s bit 1
trn tt cc cc li vo l mt s l, th hm ra ly logic 1; ngc li nu tng s bit 1 trn cc li
vo l mt s chn, th hm ra ly logic 0. C th dng cng XOR 2 li vo thc hin hm
XOR nhiu bin.
2.4.3.4 Cng ng du (XNOR)
Cng XNOR thc hin biu thc logic sau:
f = AB + AB hay f = A B = A ~ B
K hiu ca cng XNOR hai li vo c trnh by hnh 2-17.
22
=1
VVHmax
VRHmax
VVHmax
NH
3v
Vo
NL 0,4v
VVLma
1,5v
VRHmax
VRHmin
NL
VRLmax
Ra
.4
0v
VVLma
3,5v
4,9v
VRHmin
2,4v
te
0,8v
NH
ch
VVHmin
2v
VVHmin
.c
4v
1v
om
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XOR v XNOR l hai loi cng c rt nhiu ng dng trong k thut s. Chng l phn t
chnh hp thnh b cng, tr , so snh hai s nh phn v.v...
VRLmax
Ra
b) i vi h CMOS
a) i vi h TTL
0,1v
Vo
VRH
VVH
Cng I
TT
VVH
TT
Cng II
VRL
Cng I
VVL
TT
VRH
TT
Cng II
om
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VVL
VNL
.c
ch
te
.4
H s ghp ti ph thuc dng ra (hay dng phun) ca cng chu ti v dng vo (hay dng
ht) ca cc cng ti c hai trng thi H, L.
24
Cng chu ti
A
B
Cng chu ti
Cc cng ti
A
B
Cc cng ti
IRL
IRH
a) Mc ra ca cng chu ti l H
b) Mc ra ca cng chu ti l L
om
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+Vcc
ICCH
L
H
H
H
.c
ICCL
ch
te
.4
Theo thng k, tn hiu s c t l bit H / bit L khong 50%. Do , dng tiu th trung
bnh ICC c tnh theo cng thc :
Ra
Ra
tTHL
tTLH
TM TT
Trong chng 2 chng ta gii thiu v cc phng php biu din v rt gn hm Boole.
Ngoi ra cn gii thiu mt s cng logic thng dng v cc tham s chnh ca chng.
om
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CU HI N TP
Bi 2.1 Rt gn hm sau theo phng php dng bng Karnaugh:
1. F (A, B, C) = (0, 2, 4, 6,7).
a.
AB + C
b. AB + C
AB + C
d. AB + C
a.
BC + D
b. BC + ABD
BC + ABD
te
c.
ch
.c
c.
.4
d. BC + ABD
1. C D + C D . A C + D
a.
CD
b. CD
c.
CD
d. CD
2. A BC . A B + BC + C A
AB + AC
b. AB + AC + BC
c. AC + BC
a.
d. AB + BC
2.3 Rt gn hm sau theo phng php Quine-Mc.CLUSKEY:
F (A, B, C, D) = (2, 3, 6, 7, 12, 13, 14, 15).
a.
26
AC + AB
AC + AB
d. AC + AB
c.
A
B
Do u bng A+B
Do u bng B
Do u bng AB
Do u bng A+AB
om
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a.
b.
c.
d.
a.
.c
2,4 V 5,0 V?
c.
ch
te
.4
a.
b.
c.
d.
B
Hnh 1
AB + AB
AB + AB
AB + AB
AB + AB
A B = A B + AB
27
AND, OR v NOT
NAND, AND v NOT
AND, NOR v NAND
AND, OR v XNOR
0 v 0
0 v 1
1 v 0
1 v 1
ch
.c
A AND B
A XOR B
A OR B
A NAND B
.4
te
a.
b.
c.
d.
28
om
.v
a.
b.
c.
d.
om
.v
Khng bo ho.
.c
ch
Trong mch logic bo ho, cc transistor c vn hnh trong vng bo ho, cn trong cc
mch logic khng bo ho th cc transistor khng lm vic ti vng bo ho.
Cc h mch logic lng cc c bo ho l:
.4
te
PMOS.
NMOS.
CMOS
29
NI DUNG
3.1. CC H CNG LOGIC
3.1.1. H DDL
DDL (Diode Diode Logic) l h cng logic do cc diode bn dn to thnh. Hnh 3-1a,b l
s cng AND, OR 2 li vo h DDL.
+5V
A
B
om
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R1
D1
D2
a) Cng AND
D2
A
B
.c
D1
ch
R1
b) Cng OR
te
.4
Bng trng thi sau th hin nguyn l hot ng ca mch thng qua mc in p vo/ra
ca cc cng AND v OR h DDL
B (V)
F (V)
A (V)
B (V)
F (V)
0,7
0,7
4,3
0,7
4,3
4,7
4,3
A (V)
OR
AND
u im ca h DDL:
Mch in n gin, d to ra cc cng AND, OR nhiu li vo. u im ny cho
php xy dng cc ma trn diode vi nhiu ng dng khc nhau;
Tn s cng tc c th t cao bng cch chn cc diode chuyn mch nhanh;
Cng sut tiu th nh.
Nhc im :
30
+5V
D2
f
D3
4k
D1
D2
D3
Q1
+5V
om
.v
2k
4k
D1
+5V
+5V
D4
5k
.c
f
Q1
5k
b)
ch
a)
2k
.4
te
Bng cch tng t, ta c th thit lp cng NOR hoc cc cng lin hp phc tp hn. V
ti ca cc cng l in tr nn h s ghp ti (c bit i vi NH) cn b hn ch, mt khc tr
truyn lan ca h cng ny cn ln. Nhng tn ti trn s c khc phc tng phn cc h
cng sau.
3.1.3. H RTL
om
.v
B (V)
F (V)
5,7
ch
.c
.4
te
3.1.4. H TTL
32
+Vcc
R3
300
R2
1,6k
R1
4k
Q3
A
Q1
Q2
D3
A
f
Q4
R4
1k
om
.v
D2
D1
ch
.c
.4
te
+Vcc
R2
4k
R1
4k
R3
1,6k
D3
R5
1,6k
R7
130
Q7
Q6
Q4
Q1
Q2
D1
D2
D4
f
Q3
Q8
Q5
R4
1 k
R6
1 k
33
+5V
R1
4k
A
R2
1,6k
Q2
Q1
Q3
ch
.c
R3
1,6k
D1
om
.v
te
.4
Mt cng logic, ngoi hai trng thi cao v thp ti u ra ca n cn c mt trng thi
trung gian c gi l cng ba trng thi. Trng thi trung gian ny cn c tn l trng thi u ra
c tr khng Z cao hay trng thi treo. Cng c k hiu nh ch hnh 3-8.
Tng t nh cng collector h, cc h cng logic u c cng 3 trng thi. Hnh 3-8 l
mt v d v mch in ca cng NAND ba trng thi h TTL tiu chun .
A
B
E
(a)
(b)
Hnh 3-8. K hiu ca cng ba trng thi : (a) cng NOT; (b) cng AND.
Hot ng ca cng NAND 3 trng thi c gii thch bng bng trng thi 3-3. Khi trn
li vo E c mc logic thp, cng hot ng nh mt cng NAND. Trn li ra f s tn ti hai
trng thi cao v thp nh thng l.
34
+5V
R1
4k
R5
130
R3
1,6k
R2
4k
D1
R5
Q4
Q3
Q1
+Vcc
Q4
D2
Li ra Z cao
f
Q5
R4
1k
Q5
Q2
om
.v
te
-
.4
.c
ch
Cng TTL tiu chun c nhc im chung l thi gian tr truyn lan ln. Nguyn nhn
ca nhc im ny l do tt c bn dn trong mch u cng tc ch bo ho. Mt trong
nhng bin php gim nh tr truyn lan l s dng diode Schottky chng hin tng bo ho
ny.
Diode v bn dn Schottky
Cu to ca diode Schottky cng ging nh diode Silic. Nh vic chn thm mt lp oxit
kim loi vo gia tip gip p-n m in th phn cc ca n l 0,4 Vdc (thp hn 0,6 vn i vi
diode Silic v cao hn 0,2 vi diode Ge).
K hiu ca diode v bn dn Schottky cho hnh 3-10.
35
B
E
a) K hiu Diode
Schottky
b) Cu to bn dn
Schottky
c) K hiu bn
dn Schottky
om
.v
R1
8,2k
R3
R2
900
50
Q3
Q1
D2
R4
3,5k
R5
500
ch
D1
Q2
Q5
.c
Q6
R6
250
te
Q4
.4
36
1. Loi PMOS
om
.v
Mch in ca h cng ny ch dng MOSFET c knh dn loi P. Cng ngh PMOS cho
php sn xut cc mch tch hp vi mt cao nht.
Hnh 3-12 l s cng NOT v cng NOR loi PMOS. y MOSFET Q2, Q5 ng
chc nng cc in tr.
VDD
VDD
S
Q1
f=A
G
S
Q4
Q2
f= A+B
D
S
te
Q3
D
ch
D
S
.c
VSS
Q5
D
.4
VSS
b) Cng NOR
a) Cng NOT
Hnh 3-12. Mch in ca cng NOT v NOR theo cng ngh PMOS.
2. Loi NMOS
VDD
VDD
Q1
Q1
f
f
A
Q2
Q2
A
Q3
B
Q3
B
VSS
a) Cng NAND
VSS
b) Cng NOR
Hnh 3-13. Mch in cng NAND v NOR theo cng ngh NMOS.
37
om
.v
ch
.c
minh ho, ta c th tm hiu hot ng ca cng NOT. T hnh 3-14a, d thy rng, nu
tc ng ti li vo A logic thp th Q1 s thng, Q2 kho. Li ra f gn nh c ni tt ti VDD v
cch ly hn vi t, ngha l VRH VDD. Ngc li, khi A ly mc cao, Q1 m v Q2 ng. Do ,
li ra f gn nh ni t v cch ly vi VDD. Ni khc i, VRL 0.
VDD
S
Q1
D
D
.4
Q2
te
VDD
Q1
Q2
D
D
G
f
Q3
a) Cng NOT
Q4
B
b) Cng NAND
4. Cng truyn dn
Da trn cng ngh CMOS, ngi ta sn xut loi cng c th cho qua c tn hiu s ln
tn hiu tng t. Bi vy cng c gi l cng truyn dn. S nguyn l v k hiu cng
truyn dn nh hnh 3-15.
38
S
Vo/Ra
Vo/Rao
Ra/Vo
+5V
Ra/Vo
Q2
iu khin
G
b) K hiu
a) Mch in
om
.v
Mch nguyn l ca cng truyn dn cng s dng hai MOSFET c knh dn ngc nhau.
Tuy nhin cch iu khin trng thi cc chuyn mch li khc vi cng logic thng thng.
Trong trng hp ny, ngi ta phn cc sao cho khi c tn hiu iu khin th c hai chuyn
mch Q1 v Q2 cng dn in. Khi , mch tng ng nh mt dy dn. Cc cng o (trong
s k hiu) m bo cc tnh iu khin ph hp cho c hai cc G ca mi MOSFET.
.c
ch
R5
+Vcc
R8
R6
Q8
Li
vo
D
C
.4
te
Q1
R1
Q7
Q4
Q2
R2
Q3
R3
Q5
Li ra NOR
Q6
RE
Ra
- 0,9 V
D1
D2
-1,29
R4
Li ra OR
R7
- 1,75 V
R9
-Vcc = - 5V
a) Mch in nguyn l
- 1,4 V - 1,2 V Vo
b) th mc vo/ra
om
.v
ch
Rp
.c
+ 5V
Ti CMOS
.4
te
iu khin
TTL
in p cung cp dng cho IC CMOS thch hp nht l t +9V n +12V. Mt cch dng
in p cung cp ln l s dng IC TTL h mch Collector nh hnh 3-18, v tng ra ca
TTL h cc C ch gm transistor nhn dng vi cc C th ni. hnh ny cc C h c ni
vi ngun cung cp +12V qua in tr ko ln 6,8k. Khi li ra ca h TTL mc L th dng
ca n l:
Inhn dng =
12V
= 1, 76mA
6,8k
40
+ 12V
6,8k
TTL h mch
Collector
Ti CMOS
om
.v
ch
3,3k
.c
+ 12V
B chuyn mc
40109
Ti CMOS
te
iu khin
TTL
.4
Hnh 3-19. B chuyn mc CMOS cho php s dng hai loi ngun +5V v +12V.
3.2.2. Giao tip gia CMOS v TTL
iu ny c ngha l iu khin CMOS c th cho nhn dng l 360 A khi trng thi L,
l dng vo i vi IC TTL loi Schottky cng sut thp. Mt khc, iu khin CMOS c th
cho dng ngun 360 A, n ln hn mc cn thit iu khin dng vo trng thi H. Nh
vy h s ghp ti gia CMOS v 74LS l bng 1.
41
iu khin
CMOS
om
.v
Ti TTL
+ 5V
Tng m
CMOS
.c
ch
te
V ti TTL tiu chun c dng li vo trng thi L bng 1,6mA v dng li vo trng
thi H l 48 A, IC 74C902 c th iu khin hai ti TTL tiu chun.
.4
iu khin
CMOS
Tng m
CMOS
+ 5V
Ti TTL
Hnh 3-21. iu khin CMOS hot ng thch hp nht vi ngun cung cp +12V.
42
+ 12V
3,3k
Ti TTL
om
.v
Tng m
CMOS h
cc mng
iu khin
CMOS
.c
Hnh 3-22 l mch dng tng m CMOS h cc mng lm giao din iu khin CMOS v
ti TTL. in p cung cp cho hu ht cc tng m l +12V. Tuy vy c th ni tng m h cc
mng vi ngun cung cp +5V qua mt in tr ko ln (pull up) c gi tr 3,3k. Cch ni ny
c u im l c iu khin CMOS v tng m CMOS u c cung cp ngun +12V, khng
k li ra h cc mng giao din vi TTL
ch
TM TT
te
.4
C 2 loi vi mch s ph bin nht : TTL v MOS. TTL l cng ngh in hnh trong nhm
cng ngh transistor bao gm TTL, HTL, ECL, MOS l cng ngh vi mch s dng MOSFET,
trong in hnh l MOS
ng thi trong chng 3 cng a ra vn giao tip gia cc h cng vi nhau.
CU HI N TP
a. NOR
43
b. OR
c. AND
d. NAND
2. Vi mch c s nh trong cu hi 1, nhng in p logic li vo tng ng vi cc
mc logic cao v thp ln lt l 10 V v 0 V th chc nng ca mch l g?
a. NOR
b. OR
c. AND
om
.v
d. NAND
te
ch
.c
b. OR
c. AND
.4
a. NOR
d. NAND
a. Cch ly transistor Q3 v Q4
b. Dch mc in p lm cho Q3 v Q4 khng bao gi cng ng hoc cng m
44
c. Chng nhiu li ra
d. Cch ly Q4 khi mch ngoi ni vo u ra f
5. Chc nng ca mch biu din trong s nh cu hi 4 s thay i th no nu diode D3
chuyn ti chn base ca transistor Q3 (cathode D3 ni vi base Q3 cn anode ni vi
collector Q2)?
a. Q3 lun cm
b. Q3 lun m
om
.v
.c
ch
te
.4
a. Mch tr thnh cng NAND vi hai trng thi li ra nh cc cng NAND thng
b. Mch tr thnh cng NOR
45
om
.v
a. Li vo ny c tnh logic 0
b. Li vo ny c tnh logic 1
d. C ba cch tr li trn u sai
.c
ch
te
.4
a. c- C th coi l mc 1
b. c- Phi coi l mc 0
a. Tn s cng tc nhanh
b. in p ngun nui thp
c. Cng sut tiu th thp
.4
te
ch
.c
om
.v
47
om
.v
ch
.c
.4
te
Phn tip theo gii thiu v Hazard trong mch logic t hp. y l phn rt quan trng khi
thit k mch. Nu khng n hin tng ny c th dn n s lm vic sai lch ca c h
thng. Phn tch v nhn dng Hazard c ngha rt quan trng khng nhng trong tng hp cc
h logic m c trong t ng chn on trng thi lm vic ca chng.
Phn tip theo gii thiu mt s mch t hp thng dng trong cc h thng s:
- M ho v gii m cc lung d liu nh phn.
- Hp knh v phn knh chn hoc chia tch cc lung s nh phn theo nhng yu cu
nht nh nh tuyn cho chng trong vic truyn dn thng tin,
48
NI DUNG
4.1 KHI NIM CHUNG
Cn c vo c im v chc nng logic, cc mch s c chia thnh 2 loi chnh: mch t
hp v mch tun t (mch tun t c trnh by chng sau).
1) c im c bn ca mch t hp
om
.v
Cc phng php thng dng biu din chc nng logic ca mch t hp l hm s
logic, bng trng thi, s dng logic, bng Cac n (Karnaugh), cng c khi biu th bng th
thi gian dng xung.
.c
ch
Y0
Y1
Ym-1
.4
xn-1
Mch logic t
hp
te
x1
Ym-1 = fm-1(x0,x1,...,xn-1).
T , ta thy rng c im ni bt ca mch logic t hp l hm ra ch ph thuc cc bin
vo m khng ph thuc vo trng thi ca mch. Cng chnh v th, trng thi ra ch tn ti trong
thi gian c tc ng vo.
Th loi ca mch logic t hp rt phong ph. Phm vi ng dng ca chng cng rt rng.
49
Nu mch phc tp th ta tin hnh phn on mch vit biu thc, sau rt gn, ti u
(nu cn) v cui cng v li mch in.
om
.v
Thit k l bi ton ngc vi bi ton phn tch. Ni dung thit k c th hin theo tun
t sau:
.c
4- T bng trng thi c th vit trc tip biu thc u ra hoc thit lp bng Cac n tng
ch
ng;
te
Li gii:
.4
V d : Mt ngi nh hai tng. Ngi ta lp hai chuyn mch hai chiu ti hai tng, sao cho
tng no cng c th bt hoc tt n. Hy thit k mt mch logic m phng h thng ?
B
0
Biu thc ca hm l: f = A B + A B = A B
hoc
f = AB A AB B
VAC
Hnh 4-2 Mch in ca h thng chiu sng
50
B
0
1
0
1
f
0
1
1
0
om
.v
Vic thit k cc mch logic nhn chung khng phc tp, v cn c biu thc ton l ta c
th v ra c mch in v lp rp thnh h thng iu khin. Trn thc t, khng phi mch no
cng c th hot ng tt c, nguyn nhn l do cu trc ca mch t hp gy ra, hin tng
hot ng khng n nh xy ra trong mch t hp c gi l hazard.
ch
.c
te
- Hazard c th xut hin nhiu ln (theo mt chu k no hoc khng theo mt chu k
no).
.4
Nh ta bit, mt trong cc c tnh quan trng nht ca mch in khi hot ng l qun
tnh, linh ng hay s chm tr ca mch. Chnh s chm tr ny lm cho tn hiu t u vo
khng th truyn ngay tc khc ti u ra ca mch in, iu ny lm cho cc thit b iu khin
pha sau khng th c phn ng tc khc i vi tn hiu a vo. Do tt c cc mch in u c
thi gian tr nht nh, ngay c cc mch vi in t cng c thi gian tr. S thay i nhit
mi trng cng lm cho thi gian tr thay i, dn n s sai lch khi iu khin ca mch logic,
chnh l hazard.
4.4.2. Bn cht ca Hazard
hiu c nguyn nhn xut hin hazard trong mch logic t hp, hazard ch xut hin
trong mch t hp m khng xut hin bt k h thng in t no khc. Ta xt v d sau:
00
01
11
10
01
11
10
x1
x2
x3
x4
t1
Mch
logic
f(x)
om
.v
.c
te
ch
Trong trng hp ny, cc tn hiu vo (x1, x2, x3) c gi tr logic b thay i khi ta thay i
b tn hiu vo, v chng s c mt thi gian tr nht nh (c th rt nh, c s hay ns). Mt
khc, thi gian tr ca mi ng tn hiu vo (xi) li khc nhau, d cng mt chng loi IC. Nh
vy nu (x1, x2, x3) c thay i ng thi v chng c thi gian tr khc nhau th vn xy ra hin
tng "chy ua" ca tn hiu vo ti u ra ca mch in.
(x1
x2
x3
x4 )
p ng ra
f(Q) = 1
(X)
.4
V c s "chy ua" gia ba tn hiu vo (x1, x2, x3) (x4 khng thay i nn khng ua), gi
s x2 chy nhanh hn (c thi gian tr nh hn) x1, x2 (gi s thi gian tr ca hai tn hiu ny
bng nhau). Mi quan h ny ta c th biu din nh sau:
t0
'
t0
t1
f(0101) = 0
f(P) = 1
0
x2
0
Q
f(x)
P
1
om
.v
thi gian tr
t0
t'0
t1
ch
.c
te
.4
P = ( q1 , q 2 ...q k , q k +1 ,...q n )
- f(Q)=f(P)
om
.v
.c
Do c hin tng "chy ua" gia cc tn hiu vo vi nhau trong thi gian chuyn t QP
m xut hin hazard. Nu f(Q) = f(P) tc l c s thay i ca tn hiu vo nhng s iu khin
u ra ca mch logic vn khng i d l 0 hay 1, nhng xut hin hazard, khi s lng tn hiu
chy ua khng nhiu, chnh l hazard tnh.
te
ch
Hazard nht thi cng chnh l hazard tnh, tc l loi hazard ch xut hin nh mt xung
khng theo quy nh ca hm logic. Hin tng ny khng nguy him, v rng ca xung
hazard tnh t lun nh hn thi gian tr ca mch, nn mch logic vn hot ng bnh thng
d c xut hin hazard.
.4
Nhng hazard tnh nguy him ch: n c th gy ra "sai nhm" cho iu khin ca h
thng logic khi gi tr rng hazard (t) ln, iu ny s xy ra khi s "chy ua" ca tn
hiu vo qu chnh lch, ngha l c tn hiu vo "chy" qu nhanh cn tn hiu khc li "chy"
qu chm, hin tng ny c minh ho hnh 4-6.
x1, x4
0
x2
f(x)
P
t
t
0
t0 t'0
t1
54
(X)
(x1 x2
x3
x4)
t0
f(Q) = 1
om
.v
Trong thc t khi thay i tn hiu vo ca mch logic ng vi qu trnh chuyn i (QP)
c th c rt nhiu tn hiu vo cng thay i khi c s chy ua ca cc tn hiu vo ti u ra
ca mch. V d trng hp Q = (0000); P = (1101), d dng nhn thy c s chy ua (X)
t'0
f(X') = 0
"
t0
f(X") = 1
t1
.c
f(P) = 0
.4
te
ch
(X)
t
0
f(x)
0
t0 t'0
t"0 t1
55
Hazard c th xut hin do chc nng ca mch trong c hai trng hp l hm f(X) ly gi
tr logic l 0 hoc 1.
Hazard nht thi gi l hazard hm s trong thi gian chuyn i t QP nu:
- f(Q)=f(P)
- Hm f(X) ly c hai gi tr 1 v 0 trong thi gian chuyn i t QP
om
.v
.c
ch
y l loi hazard nguy him nht, hay gy ra iu khin "sai nhm" nhiu nht trong cc
h thng mch t hp iu khin.
Bn cht ca loi hazard ny nh sau:
.4
te
Khi tp tn hiu vo ca hm logic thay i ng thi nhiu bin trong thi gian chuyn i
Q P, m mi mt ln tn hiu vo c thi gian tr khc nhau, trong qu trnh "chy ua" ny
gp phi trng hp Q = (00000), P = (11101)
(X)
(x1
x2
x3
x4
x5)
t0
t0
'
"
t0
t"'0
0
0
1
1
56
f(X') = 0
1
1
0
0
f(X") = 0
f(X"') = 0
t1
f(Q) = 1
f(P) = 1
(X)
t
0
f(x)
- f(Q)=f(P)
t
t
om
.v
te
ch
.c
t0
t1
.4
Tm li, mi mt mch iu khin c th xut hin nhiu loi hazard, c mch logic c s
lng bin s "chy ua" rt ln nhng hazard li khng xut hin, nhng c mch rt n gin
th hazard li xut hin v gy ra iu khin "sai nhm". V vy mun khc phc c hazard th
phi cn c vo mch in c th ca n, ri dng k thut phn tch pht hin kh nng xut hin
hazard, sau tm cch khc phc hazard. Sau y l mt vi bin php khc phc v hn ch s
xut hin hazard trong h thng logic diu khin.
x1
x2
x3
2
Hnh 4-10. Phng php khc
phc Hazard
57
om
.v
- Tip theo khi phi chp nhn qu trnh chuyn i t QP c nhiu tn hiu thay i hay
c nhiu bin (X) chy ua. Cch khc phc l chn gi tr linh kin hay IC c thi gian tr nh.
V ta bit hazard ch xut hin trong thi gian tr ca mch, cng nh ngha l xung hazard c
rng t nh, v nh vy n khng c nng lng kch chuyn mch tip theo.Nhng khi
chn linh kin lp rp h thng hay chon IC c nh tc l phi chn linh kin, IC c cht lng
cao, ngha l gi thnh ca h iu hnh tng, y cng l vn cn quan tm khi thit mch.
.c
- Khi ta chp nhn c s chy ua tn hiu vo (X) trong qu trnh chuyn i t QP,
ng thi khng dng linh kin c cht lng cao gim gi thnh v mch vn hot ng tt
ng thi khng c hazard xut hin, th ta c th dng phng php khc phc hazard bng cch
thm cc mch tr trn ng truyn tn hiu, m bo cho thi gian chy ua ca cc tn hiu
l tng ng nhau. Phng php ny c minh ho hnh 4-10:
te
ch
Ta bit tn hiu x2 chy nhanh ti u ra, nn trn ng truyn ca x2 ta cho thm hai cng
o c thi gian tr l 1 v 2 cho tn hiu trn x2 xut hin ng thi vi x1 v x3, khi
hazard s khng xut hin hoc s lm gim bt hazard . Phng php ny c gy ra hazard nu
ng tr thm vo li lm cho x2 chy qu chm v li pht sinh hin tng chy ua tn hiu
vo.
.4
trnh xy ra hin tng chy ua tn hiu vo, cn bit chnh xc thi gian tr 1 v 2,
sau phi to ra c cng o c thi gian tr bng ng gi tr 1 v 2.
- mc cao hn khi ta phi chp nhn c s chy ua tn hiu vo trong qu trnh chuyn
i Q P, khng mun dng linh kin c cht lng cao, ng thi thm cc mch tr (khng
nh hng ti chc nng ca mch logic) nhng vn khng th khc phc ht hazard th khi ta
dng xung ng b, tc l ta bt chp c s chy ua ca tn hiu vo, v gia cc ng truyn
tn hiu t u vo ti u ra c thi gian tr khc nhau. Nhng tn hiu truyn lan trong h logic
d nhanh, d chm, n trc hay n sau th chng ch c lan truyn khi c s cho php ca
xung ng b. Xung ng b thng thng "ch" theo ng tn hiu chy chm nht, khi cc
xung n sm phi "ch" cho y cc tn hiu khc khi xung ng b mi cho php truyn
tip. Nu cho thm vo mch iu khin xung ng b th cng c th gim ng k nh hng
ca hazard.
- Trong trng hp cc phng php nu trn u c p dng nhng hin tng hazard
vn xut hin th ta buc phi thay i chc nng iu khin, tc l thay i chc nng ca hm
logic ca h thng iu khin tc l phi xy dng mch in khc.
Nh vy c c mt mch iu khin tt, cht lng cao th phn cng xy dng nn
mch in mang tnh quyt nh. Ngi thit k phi hiu rt k v su sc h thng k thut m
mnh thit k th mi c th khc phc c hazard trong mch in, cng nh phi bit thm hay
bt cc mch in ph nh th no m khng lm thay i chc nng ca h thng. T lm
58
4.5.1.1. M BCD v m d 3.
om
.v
.c
te
ch
V vy, ngi ta s dng m D-3 c hnh thnh t m NBCD bng cch cng thm 3
vo mi t hp m. Nh vy, m khng bao gm t hp ton Zero. M D-3 ch yu c dng
truyn dn tn hiu m khng dng cho vic tnh ton trc tip.
.4
4.5.1.2. M Gray.
59
Gray
Gray d 3
om
.v
0010
0000
0
0110
0001
1
0111
0011
2
0101
0010
3
0100
0110
4
1100
0111
5
1101
0101
6
1111
0100
7
1110
1100
8
1010
1101
9
1011
1111
10
1001
1110
11
1000
1010
12
0000
1011
13
0001
1001
14
0011
1000
15
Bng 4-3. M Gray v Gray d 3
Thp phn
.c
4.5.1.3. M chn, l.
ch
M chn v m l l hai loi m c kh nng pht hin li hay dng nht. thit lp loi
m ny ta ch cn thm mt bit chn/ l (bit parity) vo t hp m cho, nu tng s bit 1 trong
t m (bit tin tc + bit chn/l) l chn th ta c m chn v ngc li ta c m l.
.4
te
Mch in thc hin vic chuyn tin tc sang m, c gi l mch m ho hay mch ghi
m.
4.5.1.1. Mch m ho t thp phn sang BCD 8421
Vo
Thp
phn
1
2
3
4 Mch
5 m ho
6
7
8
9
Vo thp
phn
0
1
2
3
4
5
6
7
8
9
A
8
B
4
Ra
BCD
8421
C
2
D
1
Ra BCD
8 4 2 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
om
.v
R4
= (8,9)
A = 8 +9
C = 2 + 3 + 6 + 7 = (2,3,6,7)
ch
D = 1 + 3 + 5 + 7 + 9 = (1,3,5,7,9)
te
.4
A = 8+9 = 8 . 9
B = 4+5+ 6+ 7 = 4 . 5 . 6 . 7
C = 2 + 3+ 6 + 7 = 2 . 3 . 6 . 7
R2
R1
.c
= ( 4,5,6,7)
B=4+5+6+7
R3
+5V
4
5
6
7
8
9
D = 1+ 3 + 5 + 7 + 9 = 1 . 3 . 5 . 7 . 9
61
om
.v
Vo
Ra
Thp phn
A B C D
L1L2L3L4L5L6L7L8L9
8 4 2 1
0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 1
1 0 0 0 0 0 0 0 0
0 0 1 0
x 1 0 0 0 0 0 0 0
0 0 1 1
x x 1 0 0 0 0 0 0
0 1 0 0
x x x 1 0 0 0 0 0
0 1 0 1
x x x x 1 0 0 0 0
0 1 1 0
xx x x x 1 0 0 0
0 1 1 1
x x x x x x 1 0 0
1 0 0 0
x x x x x x x 1 0
1 0 0 1
x x x x x x x x 1
Bng 4-6. Bng trng thi ca b m ho
u tin
Theo bi, s m ho thc hin theo mc u tin t L1 n L9, khi cc tn hiu cng tc
ng th cc tn hiu c mc u tin thp khng tc dng, ngha l bt k mc logic ca n l 0
hay 1 u khng nh hng n li ra nn gi n l iu kin tu chn, k hiu l "x".
.c
ch
te
+ L5 v bng 0 ti cc li L6, L8
.4
+ L7 v bng 0 ti cc li L8
+ L9
Nn ta vit c hm D:
D = L1. L 2 . L 4 . L 6 . L 8 + L 3 . L 4 . L 6 . L 8 + L 5 . L 4 . L 6 . L 8 + L 7 . L 8 + L 9
Tng t nh vy ta vit c hm ca B, C v A nh sau:
C = L 2 . L 4 . L 5 . L8 . L 9 + L 3 . L 4 . L 5 . L8 . L 9 + L 6 . L8 . L 9 + L 7 . L8 . L 9
B = L 4 . L8 . L 9 + L 5 . L8 . L 9 + L 6 . L8 . L 9 + L 7 . L8 . L 9
A = L 8 .L 9
Mch in thc hin vic chuyn t m sang tin tc c gi l mch gii m ho.
62
D0
B gii
m nh
phn
A1
D1
An-1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
74154
A0
A1
A2
A3
Vo
A
.c
.4
a) Dng c 7 on
te
ch
D2n- 1
om
.v
E1
E2
Vo
iu
khin
Li ra
hin th ch s ca mt h m phn bt k, ta
c th dng dng c 7 on. Cu to ca n nh ch hnh 4-15.
Cc on c hnh thnh bng nhiu loi vt liu khc nhau,
nhng phi c kh nng hin th c trong cc iu kin nh
sng khc nhau v tc chuyn mch phi ln. Trong k thut
s, cc on thng c dng l LED hoc tinh th lng (LCD).
b) Mch gii m 7 on
f
e
Hnh 4-15 Cu to
dng c 7 on sng
D
C
B
A
Mch
1 gii m
2 7 on
4
8
a
b
c
d
e
f
g
63
f = (0,4,5,6,8,9),
om
.v
g = (2,3,4,5,6,8,9).
IC 7447, 74247 (Ant chung), 7448 (K chung ), 4511 (CMOS) l cc IC gii m t NBCD
sang thp phn theo phng php hin th 7 on.
.c
ch
te
.4
En
X0
X1
Xj
MUX
2n 1
X0
X1
Y- Li ra
Xj
X2n-1
X2n-1
An-1 An-2 A0
n li vo iu khin
(a) S khi
Hnh 4-17. B hp knh MUX 2n 1
64
D0
74151
Vo iu
khin
Vo
d liu
D7
om
.v
A0
A1
A2
MUX
2n 1
Chn mch
Y0
Y1
ch
En
Yj
Li vo X
E2
Y0
Y1
Yj
Li vo
Y2n-1
te
Y2n-1
.4
Vo cho
php
.c
E1
An-1 An-2 A0
n li vo iu khin
(a) S khi
..............
Y2n 1 = X.A n 1.A n 2 ...A i ...A 0
B phn knh cn c gi l b gii m 1 trong 2n. Ti mt
thi im ch c 1 trong s 2n li ra mc tch cc.
IC 74138 l b DEMUX 1 li vo d liu - 8 li ra. Hnh 420 l k hiu logic ca IC 74138.
A0
A1
A2
D
E1
E2
74138
Vo iu
khin
Vo d
liu
Y0
Y7
Vo cho
php
65
Mch cng hay (b cng) l mch s hc nh phn quan trng, v trong x l nh phn phn
ln cc php tnh c thc hin thng qua php cng.
Mch logic thc hin php cng hai s nh phn 1 bit c li nh u vo c gi l mch
ton tng. S khi tng qut ca mt mch ton tng c biu din hnh 4-21.
Si = ai bi Ci-1
C i = a i b i C i1 + a i b i C i1 + a i b i C i 1
hay
.c
Si
om
.v
Cc hm ra Si , Ci s c dng:
bi
ch
Ci
.4
a) Mch in
te
G i Pi
Ci-1
Si
Ci-1
0
0
0
0
1
1
1
1
ai
0
0
1
1
0
0
1
1
bi
0
1
0
1
0
1
0
1
Si
0
1
1
0
1
0
0
1
Ci
0
0
0
1
0
1
1
1
TT
Ci
Gi
ai bi
b) K hiu
Hnh 4-21 a, b Mch ton tng v k hiu
Mch logic thc hin biu thc li ra tng v li ra nh c trnh by hnh 4-21a v k
hiu ca n l hnh 4-21b.
4.7.2 Mch cng nh phn song song
Ta c th ghp nhiu b cng hai s nh mt bit li vi nhau thc hin php cng hai s
nh phn nhiu bit. S khi ca b cng c trnh by hnh 4-22 v c gi l b cng
song song.
S0
Si
S2
S1
B ton
tng
CRi
CVi
bi
ai
CR2
B ton
tng
CV1 CR0
CV2 CR1
b2
a2
B ton
tng
B ton
tng
b1
a1
66
CV0
b0
a0
Trong cc h thng s, c bit l trong my tnh, thng thc hin vic so snh hai s. Hai
s cn so snh c th l cc s nh phn, c th l cc k t m ho nh phn. Mch so snh c
th hot ng theo kiu ni tip hoc theo kiu song song. Trong phn ny ta s nghin cu b so
snh theo kiu song song.
om
.v
gi
ch
ai
bi
.c
gi = a i . bi + a i . bi = a i bi
te
ai
0
0
1
1
bi
0
1
0
1
gi
1
0
0
1
.4
vi
g3 = a 3 b3
g2 = a 2 b2
g1 = a 1 b1
g0 = a 0 b0
4.8.2. B so snh.
4.8.2.1. B so snh 1 bit.
f < = a i . bi
f = = a i bi
f > = a i . bi
67
ai
bi
ai
0
0
1
1
bi
0
1
0
1
f<
0
1
0
0
f=
1
0
0
1
f<
f=
f>
0
0
1
0
f>
om
.v
.c
f > = a 3 . b 3 + a 3 b 3 . a 2 . b 2 + a 3 b3 . a 2 b 2 . a1 . b1 + a 3 b 3 . a 2 b 2 . a1 b1 . a 0 . b 0
te
f>
a1
b1
.4
a2
b2
ch
a3
b3
a0
b0
Mt trong nhng b so snh thng dng hin nay l 7485. IC ny so snh 2 s nh phn 4
bit.
68
Ra
Xe Xo
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
d3
0
1
0
1
0
1
0
1
Xe
om
.v
d1
0
0
0
0
1
1
1
1
Vo
d2
0
0
1
1
0
0
1
1
Xo
To bit
chn/l
.c
Xo = d1 d2 d3
te
X o = X e = d1 d 2 d 3
ch
V biu thc ca Xo v Xe l
.4
n bit d liu
Kim tra h
chn/l
Fo
Fe
Bit chn l
(Xo, Xe)
Vo
d2 d3
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
w
d1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Fe
1
0
0
1
0
1
1
0
0
1
1
0
1
0
0
1
Ra
Fo
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
Fo = d1 d2 d3 X
Fo = Fe
69
Khi s hc: Thc hin cc php tnh s hc nh l: cng, tr, tng 1, gim 1.
4
Thanh ghi A
om
.v
S khi ca 1 n
v s hc logic ALU 4 bit
c m t hnh 4-29:
Thanh ghi B
.4
te
ch
.c
4
4
M l li vo chn
Cin
php tnh s hc hay logic.
M
(Mode)
ALU
F0, F1 l hai li vo chn
F0 Chn chc nng
chc nng. Sau khi mt
F1 (Php tnh)
php tnh s hc hay logic
4
4
c thc hin th kt qu
Ghi trng thi
s c ghi ln 1 thanh ghi,
v d thanh ghi A. Kt qu
ny c th c s dng
Hnh 4-29. S khi ca ALU 4 bit
thc hin php tnh sau. B
ALU cn to ra cc bit trng thi chuyn i thanh ghi. V d: Carry out: nu c nh; Zero: nu
kt qu php tnh bng 0.
TM TT
Trong chng ny, chng ta gii thiu mch logic t hp. Mch t hp do cc phn t
logic c bn cu trc nn. c im ca mch t hp l tn hiu u ra thi im bt k no
cng ch ph thuc vo tn hiu u vo thi im m khng lin quan n trng thi vn
c ca mch.
Mch t hp rt phong ph, ta khng th xem xt ht trong chng 4. Trng tm ca chng
ta l nm vng c im mch t hp v phng php chung khi thit k, phn tch mch t hp.
V vy, chng ta gii thiu mt cch chn lc b m ho, b gii m, b hp knh, phn knh,
mch cng, tr, mch so snhtrong qu trnh , ta xem xt phng php phn tch v thit
k mch t hp.
Khi phn tch mch t hp cho, ta c th vit ra hm logic u ra cho tng cp ca s ,
ri tin hnh ti thiu ho hm logic biu th r mi quan h gia u ra vi u vo. Cn
lu thm rng phi xem xt n hin tng Hazard- l hin tng chy ua trong mch logic v
cch khc phc hin tng ny.
70
CU HI N TP
1.
om
.v
.c
3.
ch
te
a. Hazard tnh.
b. Hazard ng.
.4
c. Hazard logic.
4.
a. Ch c mt tn hiu tc ng vo.
b. Ch hai tn hiu tc ng vo.
5.
6.
8.
om
.v
9.
.c
ch
te
10.
.4
U RA
D LIU
U VO
D LIU
(a)
72
(b)
Hnh 4-29.
11.
12.
a. b hp knh 8 vo 1 ra.
c. b hp knh 1 vo 8 ra.
d. b phn knh 1 vo 8 ra.
13.
om
.v
.c
ch
te
14.
.4
b. d liu parity l.
15.
16.
17.
c. Gi tr ca s A nh hn gi tr ca s B.
19.
om
.v
d. Gi tr ca s B ln hn gi tr ca s A.
Nu li ra A<B ca b so snh c kch hot, th:
a. Gi tr ca s A ln hn gi tr ca s B.
.c
d. Gi tr ca s B nh hn gi tr ca s A.
Mt ALU c cha:
a. Mt khi s hc.
te
b. Mt khi logic.
ch
20.
c. Mt khi so snh.
.4
74
Chng ta nghin cu v php phn tch v thit k cc mch logic t hp. Mc d rt qua
trng nhng n ch l mt phn ca cc h thng k thut s. Mt phn qua trng ca cc h
thng k thut s khc l phn tch v thit k mch tun t. Tuy nhin vic thit k cc mch
tun t li ph thuc vo vic thit k mch t hp c cp chng 4.
om
.v
.c
ch
Trong phn ny chng ta s gii thiu v cc phn t nh ca mch tun t. Cch phn tch
v thit k mch tun t n gin v phc tp.
te
NI DUNG
.4
x1
x2
z1
z2
Mch t hp
Ql
zj
W1
Wk
Mch nh
Hnh 5-1. S khi ca mch tun t.
75
X - tp tn hiu vo.
Q - tp trng thi trong trc ca mch.
W - hm kch.
Z - cc hm ra
om
.v
Trong phng trnh ton hc ca mch tun t ta thy c hai thng tin. l thng tin v
trng thi tip theo ca mch tun t v thng tin v tn hiu ra ca mch. Hai thng tin ny cng
ph thuc ng thi vo trng thi bn trong trc ca mch (Q) v tn hiu tc ng vo (X)
ca n. Ta c th vit li biu thc trn nh sau:
Z = f (Q(n), X).
Q (n +1) = f (Q(n), X)
Trong :
.c
ch
te
.4
Trig c t 1 n mt vi li iu
khin, c hai li ra lun lun ngc nhau
thm cc li vo lp (PRESET) v li
vo xo (CLEAR). Ngoi ra, trig cn c
li vo ng b (CLOCK). Hnh 5-2 l
s khi tng qut ca trig.
Phn loi:
PR
Q
Cc li vo
iu khin
Clock
CLR
Hnh 5-2. S tng qut ca mt Trig
Theo phng thc hot ng thi ta c hai loi: trig ng b v trig khng ng
b. Trong loi trig ng b li c chia lm hai loi: trig thng v trig chnh
- ph (Master- Slave).
76
TRIG
TRIG
TRIG D
TRIG T
TRIG RS
NG B
KHNG NG
TRIG JK
CHNH - PH
LOI THNG
Hnh 5-3.
5 2.1.1. Trig RS
Clock
R
om
.v
>C
R
.c
a)
b)
Hnh 5-4. S k hiu ca trig RS
Qk
Mod hot ng
Qk
Mod hot ng
Nh
Nh
Xo
Nh
Lp
Xo
Cm
Lp
Cm
te
.4
ch
R
S
S
Q
Q
R
77
om
.v
Qk
Ck
Nh
Ck
Ck
Ck
ch
.c
Mod hot ng
Xo
Lp
te
.4
Q
C
C
Q
5 2.1.3. Trig D
D
Q
C
C
Q
78
om
.v
Qk
Nhn xt: T cc bng trng thi ca cc trig trn ta thy rng: Cc trig D v RS c
th lm vic c ch khng ng b v mi tp tn hiu vo iu khin D, RS
lun lun tn ti t nht 1 trong 2 trng thi n nh. Trng thi n nh l trng thi
tho mn iu kin Qk = Q. Cn trig T v trig JK khng th lm vic c ch
khng ng b v mch s ri vo trng thi dao ng nu nh tp tn hiu vo l 11
i vi trig JK hoc l 1 i vi trig T. Nh vy, trig D, trig RS c th lm vic
c hai ch : ng b v khng ng b cn trig T v trig JK ch c th lm vic
ch ng b.
.4
te
ch
.c
> TRIG
79
C 4 loi trig c gii thiu l trig RS, JK, D v T. Trn thc t c khi trig loi ny
li c s dng nh trig loi khc. Ni dung phn ny l xy dng cc trig yu cu t cc
trig cho trc.
Vi 4 loi trig trn th c 12 kh nng chuyn i sang nhau.
om
.v
RS
JK
.c
ch
Mt trong cc phng php xy dng trig loi X t loi Y cho trc c cho s
khi hnh 5-11.
te
.4
Y = f (X, Q)
thc hin chuyn i trig loi Y sang loi X cn thc hin cc bc sau:
Xc nh h hm Y = f (X, Q) theo bng hm kch.
Ti thiu ho cc hm ny v xy dng cc s .
Mch
logic t
hp
Q
Trig
loi Y
80
Qk
RS
JK
X0
0X
01
1X
10
X1
0X
X0
om
.v
01
0
0
11
1
0
10
1
X
ch
00
0
X
JK
Q
0
1
00
X
0
te
JK
Q
0
1
.c
T bng hm kch thch trn ta thu c bng Karnaugh (bng 5-6) cho S v R vi cc bin
vo l Q, J, K.
11
0
1
10
0
0
R = KQ
.4
S = JQ
01
X
1
K
J
Bng chuyn i trng thi bao gm cc hng v cc ct, cc hng ghi cc trng thi trong,
cc ct ghi cc gi tr ca tn hiu vo. Cc ghi gi tr cc trng thi trong k tip m mch s
chuyn n ng vi cc gi tr hng v ct. Bng chuyn i trng thi c m t bng 5-6.
Tn hiu vo
V
V2
V1
Vn
Trng thi
k tip Qk
S
S1
Trng
thi
trong
om
.v
S2
:
:
Sn
.c
Vn
Tn hiu
ra - R
.4
S1
S2
:
:
Sn
Trng
thi
trong
V1
Tn hiu vo
V2
.
te
ch
Cc hng ca bng ghi cc trng thi trong, cc ct ghi cc tn hiu vo. Cc ghi gi tr
ca tn hiu ra tng ng. Bng tn hiu ra c m t bng 5-7.
C th gp hai bng chuyn i trng thi v bng tn hiu ra thnh mt bng chung gi l
bng chuyn i trng thi / ra. Lc trn cc ghi cc gi tr ca trng thi k tip v tn hiu
ra (Sk / R) tng ng vi trng thi hin ti v tn hiu vo.
Bng chuyn i trng thi v tn hiu ra c m t bng 5-8.
Tn hiu vo
V
V1
V2
Vn
S
5.3.2.
hnh trng
thi.
82
Trng
thi
trong
S1
S2
:
:
Sn
Bng 5-8. Bng chuyn i trng thi v tn hiu ra
Trng thi k
tip Sk v
Tn hiu ra R
ng.
om
.v
.c
ch
M ho trng thi
H hm ca mch
Hnh thc ho
.4
te
Bi ton ban u
83
in.
5.4.1.1. Cc bc thit k
om
.v
Sau y gii thiu thut ton xc nh phng trnh li vo kch cho cc trig t hnh
trng thi.
i vi trig Qi bt k s thay i trng thi t Qi n Qki ch c th c 4 kh nng nh hnh
5-16.
Qi = 0
ch
.c
Qi = 1
Hnh 5-14. Cc cung biu din s thay i trng thi t Qi n Qki ca trig Qi
te
.4
= (1) v (2)
om
.v
.c
ch
te
.4
5.4.1.2. V d
Q2Q3
Q1
00
0 0
01
1
11
3
10
2
Q'1
100
000
0
Q'3
Q'1Q'2Q'3
011
001
Q'2Q'3
3
Q'3
010
om
.v
.c
ch
te
10
01
Q2Q3
Q1
00
.4
Q2Q3
Q1
00
Q2Q3
Q1
00
1
01
11
10
1
10
1
x
11
D2 = Q 2 Q 3 + Q 2 Q 3 = Q 2 Q 3
D1 = Q2Q3
01
D3 = Q1 Q 3
D3 = Q1 Q 3
b) Xc nh phng trnh kch cho Trig T.
Q1 Q 2 Q 3 + Q1 Q 2 Q 3 + Q1 Q 2 Q 3 + Q1 Q 2 Q 3
Q2Q3
Q2Q3
00
01
11
10
Q1
01
11
ch
T1 = Q1 + Q2Q3
00
.c
Q1
om
.v
10
x
T2 = Q3
Q2Q3
00
01
11
10
te
Q1
.4
T3 =
Bng 5-10.
Q1
T1 = Q1 + Q2Q3
T2 = Q3
T3 = Q1
Ch khi vit cc biu thc Ton, Toff ca trig th I ta cn phi n gin cc biu thc v
a v dng:
Ton = ( T* ) Q i rt ra Ji = T*.
Toff = ( T** ) Q i rt ra Ki = T**.
Vit cc biu thc Ton, Toff cho cc trig v t xc nh phng trnh kch cho cc trig
nh sau:
87
Q2Q3
00
01
11
10
Q1
1
x
J1 = Q2Q3
11
10
10
01
11
10
x
x
.4
te
00
Q1
00
01
11
K 2 = Q3
J2 = Q 3
Q2Q3
0
Q2Q3
00
01
11
10
Q1
00
01
11
10
Q1
J3 = Q1
K3 = 1
Bng 5-11. Bng tm hm kch
K2 = Q3
J3 = Q1 ;
K3 = 1
88
K1 = 1
Q2Q3
Q2Q3
Q1
01
ch
00
.c
Q1
Q2Q3
om
.v
Biu din cc hm ny trn bng Karnaugh, s dng cc trng thi tu chn ti thiu ho
. Cc trng thi tu chn bao gm 3 s khng nm trong phm vi m 5, 6, 7. Ngoi ra cn mt s
trng thi khc tu vo tng bng. V d, i vi bng tnh J1 gi tr tu chn ngoi 3 s trn cn
thm c gi tr Q1 = 1, bng tnh K1 c thm cc c gi tr Q1 = 0, tng t nh vy vi cc
bng cn li.
Q2Q3
Q2Q3
00
01
11
10
S1 = Q2Q3
Q2Q3
x
x
01
11
.4
00
10
x
te
S2 = Q 2 Q 3
11
Q1
00
.c
01
ch
00
01
11
10
x
Q2Q3
Q1
00
R1 = Q1 hoc R1 = Q 2 hoc R1 = Q 3
Q 2Q 3
Q1
Q1
om
.v
Q1
11
10
1
x
01
11
10
R2 = Q2 Q3
Q2Q3
10
Q1
00
x
R3 = Q 2 Q3
S3 = Q1 Q 3
01
; R1 = Q1 hoc R1 = Q 2 hoc R1 = Q 3
S2 = Q 2 Q3 ; R2 = Q2 Q3
S3 = Q1 Q 3
; R3 = Q 2 Q3
Cc bc thc hin:
89
Sk
Q2Q3
Q1
00
01
11
10
Qk
RS
JK
X0
0X
01
1X
10
X1
0X
X0
ch
Q1
Q2
Q3
Qk 1
Qk2
Qk3
te
a) Bng chuyn
i trng thi
D2
D3
T1
T2
T3
R1S1
R2S2
R2S3
J1K1
J2K2
J3K3
X0
X0
01
0X
0X
1X
X0
01
10
0X
1X
X1
X0
0X
01
0X
X0
1X
01
10
10
1X
X1
X1
10
X0
X0
X1
0X
0X
X XX XX XX XX XX XX
.4
D1
.c
om
.v
X XX XX XX XX XX XX
X XX XX XX XX XX XX
Bi ton phn tch l bi ton xc nh chc nng ca mt mch cho trc. Khi tin hnh
phn tch cn tun theo cc bc sau:
om
.v
.c
- Lp bng trng thi, bng ra nh phn l bng biu din mi quan h trng thi k tip,
tn hiu ra nh phn vi trng thi hin ti v cc tn hiu vo tng ng .
ch
te
mch.
5.5.1.2. V d.
.4
Q0
J0 Q 0
>
>
1
K0 Q 0
Clock
J1 Q 1
X
Q0
K1 Q1
Q0
Q1
Hnh 5-17a)
om
.v
Q0k = J 0 Q0 + K 0 Q0 = Q1 Q0
Q1k = J1 Q1 + K1 Q1 = Q0 Q1 + X + Q0 Q1 = Q0 Q1 + X Q0 Q1
te
X=0
Q0Q1
01
10
00
00
.4
S0
S1
S2
S3
Q0Q1
00
01
11
10
Tn hiu ra
ch
Trng thi
hin ti
.c
X=1
Q0Q1
01
11
00
00
X=0
Z
0
0
1
0
X=1
Z
0
0
1
0
S0
S1
00
01
X
011
011
Clock
ch
Z = C Q1 Q0
.c
om
.v
Tm li, mch cho s trn c chc nng kim tra dy tn hiu vo X dng chui c
di bng 3. Nu chui tn hiu vo c dng l 1 trong 4 dy: 010, 011, 110 v 111 mch s cho
tn hiu ra Z = 1 ti thi im c xung nhp th 3. rng ca tn hiu ra Z bng rng xung
nhp (Z = C Q1 Q0).
Z = Q1 Q0
te
.4
Vic ti thiu ho trng thi ch yu da vo khi nim trng thi tng ng. Cc trng
thi tng ng vi nhau c th c thay bng mt trng thi chung i din cho chng.
Bc 4: M ho trng thi.
Thit k mch tun t thc hin nhim v kim tra dy tn hiu vo dng nh phn c
di bng 3 c a vo lin tip trn u vo X. Nu dy tn hiu vo c dng l 010 hoc
011 hoc 110 hoc 111 th Z = 1. Cc trng hp khc Z = 0.
om
.v
.c
ch
te
trng thi S3 v chuyn n trng thi S4 khi c tn hiu X . Ck. Tng t ta xy dng c
hnh sau 5-18 a.
.4
S0
S2
S1
S3
S4
S5
S6
Z=1
Z=1
Nu mch 1 trong 4 trng thi S3, S4, S5, S6: khi c tn hiu vo X. Ck hoc X . Ck th
mch s chuyn v trng thi ban u S0. Khi dy tn hiu vo l 110 hoc 111 (ng vi ng
chuyn i trng thi l S0 S1 S3 S0) hay khi dy tn hiu vo l 010 hoc 011 (ng vi
ng chuyn i trng thi l S0 S3 S5 S0) th mch s cho tn hiu ra Z = 1 ti thi im
xung th 3. Vi cc ng chuyn i khc Z = 0.
T hnh trng thi ta xy dng c bng chuyn i trng thi nh sau:
94
Sk
X=0
X=1
X=0
X=1
S0
S2
S1
S1
S4
S3
S2
S6
S5
S3
S0
S0
S4
S0
S0
S5
S0
S0
S6
S0
S0
om
.v
.c
ch
Trng thi Si c gi l trng thi tng ng vi trng thi Sj (Si Sj) khi v ch khi:
nu ly Si v Sj l hai trng thi ban u th vi mi dy tn hiu vo c th chng lun cho dy tn
hiu ra ging nhau.
te
Nhm cc trng thi tng ng phi c nhng hng trong bng trng thi cng
mt ct (ng vi cng mt t hp tn hiu vo) l tng ng. Ngha l ng vi
cng mt t hp tn hiu vo cc trng thi k tip ca chng l tng ng.
.4
Quy tc Caldwell:
Nhng hng (tng ng vi trng thi trong) ca bng chuyn i trng thi v tn hiu ra
s c kt hp vi nhau v c biu din bng mt hng chung - c trng (trng thi c
trng) cho chng nu nh chng tho mn hai iu kin sau:
1. Cc hng tng ng trong ma trn ra ging nhau.
2. Trong ma trn ra, cc hng tng ng phi tho mn 1 trong 3 iu sau:
-
Sau khi thay th cc trng thi tng ng bng mt trng thi chung c trng cho
chng, lp li cc cng vic tm cc trng thi tng ng khc cho n khi khng th tm c
95
S
S1
Z=0
S1
Z=0
Z=0
Z=0
Z=0
S35
Z=1
S0
Z=1
S0
Z=0
Z=0
ch
S0
S0
Z=0
S0
S0
S46
Z=1
S35
S46
S35
S0
S0
Z=0
Z=0
Z=0
Z=1
S46
S12
S35
S46
S12
S12
Z=0
S35
S46
S2
S0
om
.v
S2
.c
S0
Z=0
Z=0
.4
te
Bc 4: Sau khi gp hai trng thi S1 v S2 thnh trng thi chung S12 th mch ch cn 4
trng thi S0, S12, S35, S46. M ho 4 trng thi ny bng hai bin nh phn Q1 v Q0.
Q1
M ho S
S0
S12
S35
S46
Q0
Bc 5: Xc nh h phng trnh ca
mch.
C hai cch xc nh h phng trnh
00
S0
S12
01
X
X
S46
10
11
S35
Z=1
ny.
Cch 1:
Da vo bng chuyn i trng thi ta lp bng hm kch 5-13 cho hai trig Q0 v Q1.
96
Cc u vo ca trig
X=1
Q0Q1
Q0Q1
Q0Q1
J0
K0
J0
K0
J1
K1
00
01
01
Z=0
Z=0
10
11
Z=0
Z=0
00
00
Z=1
Z=1
00
00
Z=0
Z=0
10
X=0
X=1
J1
K1
om
.v
11
X=1
ch
01
X=0
.c
X=0
Trng
thi hin
ti
01
11
10
00
01
11
10
00
0
1
Q0Q1
.4
Q0Q1
te
K0 = 1
J0 =Q1
Q0Q1
00
01
11
Q0Q1
00
01
11
10
10
K1 = X + Q 0
J1 = Q 0
Q0Q1
X
00
01
11
10
Z = X Q0Q1
97
JQ = T*
J 0 = Q1
K 0 =1
TonQ1 = S0 X = Q0 Q1
J1 = Q0
om
.v
J0 Q 0
K0 Q 0
>
K1 Q1
Q0
Q1
Q0
te
Clock
Q1
ch
>
1
J1
K1 = Q 0 X + Q 0 = X + Q 0
.c
Q1
i vi trng hp ny ta c:
.4
Vic thit k mch tun t khng ng b dng cc trig loi khng ng b khc hon
ton tng t.
5.6.1. Cc bc thit k mch tun t khng ng b
om
.v
+ Lp bng chuyn i trng thi v tn hiu ra, t xc nh cc phng trnh kch cho
cc trig.
.c
+ Da trc tip vo hnh trng thi, vit h phng trnh Ton, Toff ca cc trig v
phng trnh hm ra.
ch
te
Bc 6: V s thc hin.
.4
99
SA = 2 (A , N , X1, X2Xm )
om
.v
RA = 1 (A , N , X1, X2Xm )
.c
SA = tp hp bt ca A + [(1)]
RA = tp hp tt ca A + [(0)]
ch
te
.4
Ak = S A + R A A
Qk = S + R Q
SA = 2A (A , N , X1, X2Xm )
RN = 1N (A , N , X1, X2Xm )
SN = 2N (A , N , X1, X2Xm )
Z1 = 1 (A , N , X1, X2Xm )
Z2 = 2 (A , N , X1, X2Xm )
100
X2
om
.v
X1
Li vo
Mch logic
.c
ch
te
.4
X1 X 2
X1 X 2
X1 X 2
S0
Trng
thi tnh
X1X2
S3
X1 X 2
X1 X 2
X1 X 2
X1 X 2
X 1X 2
X1 X 2
Z=1
S2
ng vo
S4
ng ra
Hnh 5-19 c) hnh trng thi
Trng thi
hin ti
S0
X1
0
S1
Z=0
S3
S2
Z=0
S0
S3
Z=0
X2
0
Z=0
S2
S2
X1
1
Z=0
S0
S4
X2
1
S1
Z=0
S3
X1
1
S3
Z=0
S1
X2
1
Z=0
S0
X2
0
om
.v
X1
0
S1
Z=1
Z=0
S4
Z=0
S3
Z=0
S4
Z=0
.c
Z=0
S1
Z=0
ch
te
.4
Trong bng chuyn i trng thi, nhng c khoanh trn l nhng c trng thi k
tip bng trng thi hin ti. Nhng trng thi l nhng trng thi n nh. iu kin cho trng
thi n nh l Sk = S.
Trng thi
hin ti
S012
X1
X2
0
0
S012
Z=0
S012
Z=0
X1 X2
1
1
S012
Z=0
Z=0
S34
S34
Z=0
Z=0
X1
0
S34
X2
1
X2
X1
1
0
S012
Z=0
S012
Z=0
S34
om
.v
X1 X 2
S012
S34
Z = X1X2
A=0
A=1
.c
X2
ch
te
.4
RA = A X 2 + A X 1 X 2 + A X 1 X 2 = X 2
Q k = S A + RA QA
Thay gi tr ca RA, SA vo biu thc thu c kt qu:
Ak = X 1 X 2 + X 2 A = X 1 X 2 + X 2 A = X 1 X 2 . X 2 A
Phng trnh ra:
103
Z k= A XA1 X 2
X1
X1
X2
A
X2
X1
om
.v
X2
X2
S A = X1 X 2
RA = X 2
ch
.c
te
i vi mch tun t ng b, vic m ho trng thi l lm sao cho s thc hin mch
l n gin nht.
.4
i vi mch tun t khng ng b, trong mch thng xy ra cc hin tng hoc l chu
k hoc l chy ua. Nhng hin tng ny lm cho mch hot ng sai lch i so vi chc nng
ca n. V vy, khi m ho trng thi ca mch tun t khng ng b ta phi trnh cc trng
hp .
Si2
Si3
Sin
Trn bng trng thi hin tng chu k c th hin ch: ct ng vi t hp tn hiu vo
khng c trng thi no c khoanh trn (khng c trng thi no n nh).
104
X+X
S3
X+X
S2
S0
S2
S1
S1
S2
S2
S2
S3
S3
S3
S3
S0
om
.v
Gi thit ban u mch trng thi S3 (AB = 10) v X = 0. Sau tn hiu vo X thay i
t 0 n 1 th mch s chuyn trng thi t S3 sang S0. Nu X vn bng 1 th mch s ln lt
chuyn n cc trng thi tip theo l S1, S2, S0. Khi X = 1 chu trnh chuyn i trng thi nh
hnh 5-21:
X
S0
S1
X
S
0
1
S2
ch
.c
S0
S3
.4
nh ngha:
te
Hin tng chy ua trong mch khng ng b l hin tng: do tnh khng ng nht
ca cc phn t nh phn dng m ho trng thi, v mch hot ng khng ng b, khi mch
chuyn trng thi t Si Sj mch c th chuyn bin trng thi theo nhng con ng khc nhau.
V d: Chy ua khng nguy him: Mt mch tun t khng ng b c bng trng thi m
t hnh 5-22 .
Nhn vo bng ta thy nu mch ang trng thi S0 (AB = 00) tn hiu vo X thay i t 0
1 mch s chuyn trc tip ti trng thi S2 (AB = 01) v nu X vn bng 0 trng thi tip
theo ca mch s l S3, n s l trng thi n nh cui cng ca mch nu nh X vn bng 0.
Mch c th thay i trng thi theo nhng con ng khc nhau tu thuc vo th t thay
i (hay thi gian qu ) ca A v B
105
A thay i
trc B
AB S
00 S0
S2
S1
01 S1
S2
S2
11 S2
S3
S3
10 S3
S3
S0
B thay i
trc A
A, B cng
thay i
om
.v
.c
ch
Khi mch ang trng thi n nh (trng thi c khoang trn), n ch thay i trng thi
khi tn hiu vo thay i.
S0
11
10
S3
S1
.4
AB
te
Chy ua nguy him: hnh trng thi ca mch khng ng b m t hnh 5- 23a.
X 01
S2
S AB
S0
00
S0
S1
S2
01
S0
S2
S1
11
S2
S1
S3
10
S3
S3
B thay i trc
A, B thay i
ng thi
A thay i trc
Ti thiu ho trng thi l gim bt s trng thi (nu c th) mch thit k l n gin
v do vy tin cy hn.
i vi cc trng trong bng chuyn i trng thi (nhng ny ng vi t hp tn hiu
vo khng xut hin) c th ly gi tr tu chn kt qu ti thiu ho l ti gin.
om
.v
.c
trnh hin tng chy ua, phi m ho trng thi sao cho vi tt c cc chuyn i
trng thi c th c ca mch ch c duy nht mt bin thay i.
V d. hnh trng thi ca mch tun t khng ng b c m t nh hnh 5-24:
S0
S1
ch
AB
00
AB
00
S0
te
.4
w
S2
11
S1
01
01
11
10
S3
S2
om
.v
m.
5.8.1.1. nh ngha v phn loi b m
1. nh ngha.
ch
.c
te
B m
H s m = M
.4
Hnh 5- 25 S khi ca b m
X / 0
1
X / 0
X / 0
M-2
M-1
X / 1
Khi khng c tn hiu vo m (X) mch gi nguyn trng thi c, khi c tn hiu m th
mch s chuyn n trng thi k tip.
Tnh cht tun hon ca b m th hin ch: sau M tn hiu vo X th mch li quay tr
v trng thi xut pht ban u.
Tn hiu ra ca b m ch xut hin (Y = 1) duy nht trong trng hp: b m ang
trng thi M - 1 v c tn hiu vo X. Khi b m s chuyn v trng thi 0.
108
C nhiu cch phn loi b m. Hnh 5-27 l cch phn loi in hnh ca b m.
ng b
Phn theo cch hot ng
Khng ng b
m tin
m li
M = 2N
om
.v
Phn theo h s m
B
m
M 2N
Khng lp trnh
ch
.c
Phn theo cc to M
Phn theo m
te
Lp trnh
M nh phn
M NBCD
M Gray
M Johnson
M vng
.4
5.8.1.2. Cc bc thit k b m
Xc nh s trig ca b m (n) M
ho trng thi theo m cho
S
Hnh 5-28. Cc bc thit k b m
109
Thit k b m nh phn ng b c M = 4.
Do M = 4 nn lp c hnh trng thi hnh 5-29.
S0
Q 1Q 0
S1
S2
S3
00
01
10
11
Hnh 5-29
n +1
Trig Q1
om
.v
Q1 Q0 Qk1 Qk0 R1 S1 J1 K1 T1 R0 S0 J0 K0 T0
0
ch
.c
Bng 5-16
R0 Q0
R1 Q1
>
>
S0 Q 0
S1 Q 1
.4
te
Clock
'1'
J0 Q 0
J1 Q 1
>
>
K0 Q 0
K1 Q 1
'1'
T0 Q0
T1 Q1
>
>
Q0
Clock
Clock
i vi trig Q0:
R0 = Q0; S0 = Q 0
110
Q1
Thit k b m ng b c M = 5.
om
.v
A. 2. B m c mod m bt k
S2
000
0 01
010
S3
S4
011
100
.c
S0
Q2 Q1Q0
te
ch
Qk1
Qk0
J2
K2
J1
K1
J0
K0
.4
Q2 Q1 Q0
Qk2
J1 = K1 = Q0;
J2 = Q1Q0 ; K2 = 1;
Kim tra kh nng t khi ng bng bng 5-18.
Nhn vo bng trng thi 5-18, ta thy cc trng thi d sau 1 s xung nhp u quay tr li
vng m nn ta ni b m ny t khi ng.
111
n+1
Q2
Q1
Q0
Qk2
Qk1
Qk0
J1 Q 1
>
>
K1 Q1
K0 Q 0
J2 Q 2
om
.v
'1'
J0 Q 0
>
'1'
Clock
K2 Q 2
.c
ch
B. B m khng ng b.
B. 1. B m nh phn
te
Cc b m ny c s rt n gin vi c im:
.4
Clock
J0 Q 0
'1'
K0 Q 0
'1'
'1'
K1 Q1
J2 Q 2
>
>
>
'1'
J1 Q 1
'1'
K2 Q 2
112
V d: Thit k b m M = 5 khng ng b.
T yu cu bi ton ta xy dng s khi v hnh trng thi nh hnh 5-34.
Li ra
C
M = 5
Xung m
S0 S1 S2 S3 S4
a) S khi ca b m Mod 5
om
.v
.c
Q0
ch
Q1
te
Q2
C1 = C ; C2 = Q0 ; C3 = C;
Q1Q0
.4
- Tm h phng trnh:
Q1Q0
00
01
11
10
Q2
00
01
11
10
001
010
100
011
000
Qk0 = Q 2 Q 0
Q2
Q1Q0
Q1Q0
Q2
00
01
11
10
Q2
00
01
11
10
Qk1 = Q1
Qk2 = Q 2 Q1 Q0
113
Q1
Q0
Qk2
Qk1
Qk0
om
.v
Q2
.c
Nhn vo bng 5-20, ta thy cc trng thi d sau 1 s xung nhp u quay tr li vng m
nn ta ni b m ny t khi ng.
ch
te
J1 = K1 = 1;
J2 = Q1Q0 ; K2 = 1;
.4
J0 Q 0
'1'
K0 Q 0
>
>
>
'1'
J2 Q 2
J1 Q 1
'1'
K1 Q1
'1'
K2 Q 2
Clock
D0 Q0
D1 Q1
D2 Q2
D2 Q2
>
>
>
>
Q2
Q1
Q0
Q3
Clock
om
.v
Vo ni tip, ra song song: thng tin c a vo thanh ghi dch tun t tng bit
mt, s liu c a ra ng thi tc l tt c n trig ca thanh ghi c c cng
mt lc.
te
ch
.c
.4
B ghi dch c s dng rng ri nh d liu, chuyn d liu t song song thnh ni
tip v ngc li. B ghi dch l thnh phn khng th thiu c trong CPU ca cc h vi x l,
trong cc cng vo/ra c kh nng lp trnh.
115
Trong phn ny ta gii thiu b ghi dch 4 bit np vo ni tip hoc song song, ra ni tip
v song song, dch phi.
S b ghi dch ny c trnh by trn hnh 5- 37.
om
.v
TM TT
1-
.c
Khc vi mch logic t hp, mch logic tun t c tn hiu u ra ph thuc khng nhng
tn hiu u vo thi im xt m c vo trng thi mch in sn c thi im . y l c
im chc nng logic ca mch tun t. nh trng thi mch in, mch tun t phi c phn
t nh - l cc trig.
2-
te
ch
Trig l linh kin logic c bn ca mch s. Trig c hai trng thi n nh, di tc dng
ca tn hiu bn ngoi c th chuyn i t trng thi n nh ny sang trng thi n nh kia, nu
khng c tc dng tn hiu bn ngoi th n duy tr mi trng thi n nh vn c. V th, trig c
th c dng lm phn t nh ca s nh phn.
Quan h gia chc nng logic v hnh thc cu trc ca trig
.4
Chc nng logic v hnh thc cu trc ca trig l hai khi nim khc nhau. Chc nng
logic l quan h gia trng thi tip theo ca u ra vi trng thi hin ti ca u ra v cc tn
hiu u vo. Do chc nng logic khc nhau m trig c phn thnh cc loi RS, D, T, JK. Cn
do hnh thc cu trc khc nhau m trig li c phn thnh loi trig thng v loi trig chnh
ph.
Mt trig c chc nng logic xc nh c th thc hin bng cc hnh thc cu trc khc
nhau. V d, cc trig cu trc loi chnh ph v loi thng u c th thc hin chc nng ca
mt trig khc. Ngha l cng mt cu trc c th m trch nhng chc nng khc nhau.
Mch tun t c th c rt nhiu chng loi. Chng ny ch gii thiu mt s loi
3mch tun t in hnh: b m, b ghi dchng thi vi vic nm vng cu trc, nguyn l
cng tc v c im ca cc mch tun t , chng ta cng phi nm vng c c im
chung ca mch tun t v phng php chung khi phn tch v thit k mch tun t.
CU HI N TP CHNG 5
1. Cho cc trig c bn loi RS, JK, D v T. Loi trig no trong s cc loi ny c th
thc hin c m khng cn tn hiu ng b.
a. Trig RS v trig D.
116
d. Trig JK.
om
.v
.c
ch
te
.4
a. 2000 hz.
b. 1000 hz.
c. 100 hz.
d. 500 hz.
om
.v
a. Trig D.
b. Trig RS.
c. Trig JK.
.c
a. 2.
ch
b. 3.
c. 4.
te
d. 5.
.4
a. B m vng.
b. B m vng xon.
c. B m nh phn.
CC LI RA HOT
NG MC THP
om
.v
CC LI VO PHT XUNG
HOT NG MC CAO
CC LI RA D LIU
HOT NG MC THP
CC LI VO D LIU
HOT NG MC CAO
HOT NG MC THP
.c
Hnh 1
a.
ch
c.
te
b. lp tt c 6 li ra ca IC.
Ch xo cc li ra t QD n QA.
.4
d. Ch xo cc li ra CARRY v BORROW.
16. Nu cc li vo ca LS 193 c gi tr l 1010, th cc li ra ca b m s l:
a. 32.
b. 16.
c. 8.
.c
om
.v
ch
a. 4.
b. 2.
te
c. 10.
d. 16.
.4
a. 100 KHz.
b. 50 KHz.
c. 12,5 KHz.
d. 6, 25 KHz.
120
om
.v
.c
ch
te
.4
a. Tt c cc u ra thay i ng thi.
b. Mt tn hiu xung nhp iu khin tt c cc trig.
c. Tt c cc u ra l o.
d. Cc trig trong b m hot ng theo phng php chui cnh hoa (daisy-chaind).
(iu ny c ngha l li ra ca trig trc s iu khin li vo ca trig sau).
29. H s chia tn s cho mt b m khng ng b 4 bit l :
a. 1, 2, 4 v 8.
b. 1, 2, 4 v 16.
c. 2, 4, 8 v 16.
d. Tt c cc trng hp trn, ph thuc vo tn s xung clock.
121
a. 32.
om
.v
b. 16.
c. 8.
d. Khng c trng hp no trn.
.c
ch
c. Ni tt c cc li vo J, K, CLR v PR vi VCC.
d. S dng bt k cu trc no trn.
J1 Q 1
J2 Q 2
>
>
K1
K2 Q
.4
J0 Q 0
te
>
'1'
K0 Q
Hnh 2
Clock
a. Mod 5.
b. Mod 6.
c. Mod 7.
d. Mod 8.
J0 Q 0
Clock
122
'1'
>
'1'
K0 Q 0
'1'
J1 Q 1
J2 Q 2
>
>
K2 Q 2
K1 Q1
'1'
Hnh 3
a. Mod 5.
b. Mod 6.
c. Mod 7.
J1 Q 1
>
>
K0 Q
K1
J2 Q 2
>
Hnh 4
.c
K2 Q
ch
'1'
J0 Q 0
om
.v
d. Mod 8.
a. Mod 5.
.4
b. Mod 6.
te
Clock
c. Mod 7.
d. Mod 8.
c t mc thp.
b.
c.
d.
c t mc cao.
39. Nu mch ca bn c thit k dch tri d liu vo ni tip, sau lung bit d
liu chuyn ng t:
a. Tri qua phi.
b. T phi qua tri.
123
.4
te
ch
.c
om
.v
124
om
.v
C ba loi b a hi:
B a hi n n (mt nhp).
.c
.4
te
ch
NI DUNG
6.1. MCH PHT XUNG
6.1.1. Mch dao ng a hi c bn cng NAND TTL
om
.v
Cng NAND khi lm vic trong vng chuyn tip c th khuch i mnh tn hiu u vo.
Nu 2 cng NAND c ghp in dung thnh mch vng nh hnh 6-1 ta c b dao ng a
hi.VK l u vo iu khin, khi mc cao mch pht xung, v khi mc thp mch ngng
pht.
ch
.c
.4
te
Khi , cng I nhanh chng tr thnh thng bo ho, cng II nhanh chng ngt, mch bc
vo trng thi tm n nh. Lc ny, C1 np in v C2 phng in theo mch n gin ho c
th hin trong hnh 6-2. C1 np n khi Vi2 tng n ngng thng VT, trong mch xut hin qu
trnh phn hi dng nh sau:
126
V H2
V H2
EC
R f2
R1
R f2
V L1
EC
R1
V i2
C1
V i2
V L1
+
-
C1
-
R f1
V H2
V H2
C2
V L1
V i1
R f1
V i1
om
.v
V L1
C2
.4
te
ch
.c
V thi gian np in nhanh hn thi gian phng, nn thi gian duy tr trng thi n nh
tm thi ph thuc vo thi gian np in ca hai tu in C1 v C2. T hnh 6-2 ta c thi gian np
in ca tu C1 l 1 = (Rf2 // R1) C1, thi gian Vi2 np in n VT l:
t M 2 = (R f 2 // R 1 )C1 ln
T 2(R f // R 1 )C
T l chu k ca tn hiu a hi li ra.
127
ch
.c
om
.v
te
.4
Hnh 6-7a l mch dao ng a hi c bn s dng hai cng NOR CMOS v cc linh kin
nh thi tr v t. Gin xung ca mch c th hin trn hnh 6-7b. Chu k dao ng ca
mch c tnh gn ng nh sau:
128
om
.v
ED
E
+ D
T = T1 + T2 = RC ln
E D VT VT
Nu gi thit VT = ED/2 th T1 = T2, khi T = RCln4 1,4RC.
.c
D1
T2
.4
D0
u vo
R5
R3
Mch Schmit
R7
T4
D3
T1
te
Vi
R2 R4
ch
R1
EC
Vo
T 3 D4
T5
R6
u Ra
129
ch
.c
om
.v
Kt qu mch in nhanh chng lt sang trng thi T1 ngt, T2 thng bo ho. Chng ta gi
gi tr in p u vo VI trong qu trnh tng ln ca n t n ngng lm lt mch schmit
u ra t mc cao xung mc thp l ngng trn VT+ v gi tr ngc li l ngng di ca
trig schmit VT-(hnh 6- 9). Hiu in p tng ng vi ngng trn v ngng di c gi l
chnh lch in p chuyn mch V = VT+ - VT-.
te
.4
Trig schmit thc cht l mt b so snh hai ngng nn n c dng ng dng khc nhau
nh: Cc mch dao ng, cc mch so snh, lc nhiu v.v..
6.3. MCH A HI I
Vo1
VI
V i2
Vo
130
ED
VI
ED
VO1
ED
VT
ED
VO2
om
.v
VI2
TW
.c
te
ch
Hnh 6-10 l s nguyn l ca mach a hi i kiu vi phn. Ti trng thi n nh, VI=0
th VO1=ED, VI2=ED, VO2=0. Khi c mt xung kch thch li vo lm cho cng 1 nhanh chng cm
v li ra bng 0, xem gin 6-11. Mch in RC s np in cho t in C. Trong qu trnh np,
in p VI2 tng dn n ngng VT v lm cng 2 ng, in p VO2=0. Khi , cng 1 nhanh
chng chuyn v trng thi cm v lm cho mch a hi i tr v trng thi n nh.
.4
TW = ( R + R0 ) C ln
ED
ED VT
131
ED
VI
VO1
VI2
VT
om
.v
VO
TW
ch
.c
Hnh 6-12 biu din s nguyn l ca mch a hi i kiu tch phn. Ti trng thi n
nh, VI=1 th VO1=0, VI2=0, VO2=0. Khi li vo VI chuyn t 1 xung 0 li ra VO2 nhy t trng
thi 0 ln 1 v ng thi mch RC bt u tch in cho t in C, khi in p VI2 = VT in p li
ra VO2 chuyn xung trng thi 0. Sau khi khi ht xung li vo t in phng in thng qua tr R
v mch tr v trng thi n nh.
te
TW = ( R + R0 ) C ln
ED
ED VT
.4
TW = RC ln
ED
ED VT+
nu VT=ED/2 th TW = 0, 7 RC
VI
ED
R
VI
Vo
VT+
Vo
TW
132
om
.v
trng thi tm n nh. Do Q = 0 kho cng 4, nn sau khi b kch thch bi sn dng xung P
th mch b cch ly khi xung P.
E C =5V
P'
.c
ch
V1
V2
V3
te
.4
V in p trn t C khng tng t bin nn khi V1 t mc cao 3,6 V t bin xung 0,3 V
th V2 t mc 0,7 V t bin xung -2,6 V. Bt u qu trnh np in ca t in C. V2 tng dn
ln. Khi V2 Tng ln n ngng thng 0,6 V th sinh ra qu trnh phn hi dng sau:
V2 V3 V1 Q
133
V1
om
.v
V2
ch
.c
V3
t (t pd )
te
.4
6.4. IC NH THI
Chn
Chn
Chc nng
t - GND
in p iu khin
Chn ngng
u ra
u phng in
Xo - Reset
Ngun - Vcc
TRIG
X
1
> EC
3
1
> EC
3
1
> EC
3
R
L
OUT
DIS
Thng
Thng
H
H
Khng i Khng i
H
Ngt
8
5K
So snh 1
B iu
khin
Trig
So snh 2
Tng
cng sut
li ra
5K
.c
om
.v
5K
ch
te
1) Trig Schmitt
.4
E C1
E C2
R4
R1
VI
R2
R3
VO2
VO1
135
Hnh 6-19 l s nguyn l v gin thi gian ca mch a hi i dng IC 555, trong
RC l mch nh thi. ko di xung li ra c xc nh bng cng thc
TW RC ln 3 1,1RC . Mch dao ng a hi i ny yu cu rng xung li vo nh hn
rng xung li ra, nu n ln hn th yu cu dng thm mch vi phn li vo.
VC
2E C / 3
EC
om
.v
VO
EC
VI
TW
.c
2E C / 3
EC
ch
VC
R1
2E C / 3
EC
VO
te
0,01 F
R2
.4
VC
TM1
TM2
VO
TM 1 = ( R1 + R2 ) C ln 2 = 0, 7 ( R1 + R2 ) C
TM 2 = R2C ln 2 = 0, 7 R2C
T = TM 1 + TM 2 = 0, 7 ( R1 + 2 R2 ) C
f = 1/ T =
1, 43
( R1 + 2 R2 )C
EC
4
R1
0,01 F
555
3
VO
R2
om
.v
VC
TM TT
ch
.c
Trong chng ny chng ta tm hiu cc mch to xung. Mch dao ng xung t kch
khng cn tn hiu ngoi a vo; sau khi c cp ngun mt chiu mch t ng sinh ra xung
vun. Thuc loi dao ng t kch ny c cc mch: b dao ng a hi c bn cng NAND h
TTL, b dao ng vng, b dao ng thch anh, b dao ng a hi c bn CMOS.
te
Mch to dng xung khng t ng pht xung nhng c th bin tn hiu u vo hnh dng
khc thnh xung vung theo yu cu ca mch s. Trong s mch to dng xung, chng ta tm
hiu: trig Schmit v n n.
.4
Cch mch pht xung v to dng xung trn y, ngoi dng lm xung ng h ra cn c
ng dng vo cng rng ri trong cc h thng xung - s. B dao ng a hi thng dng lm b
to xung chun thi gian v chun tn s. Mch n n thng dng nh thi v lm tr xung.
Trig Schmit ngoi ng dng to dng xung cn ng dng so snh mc v gim st mc
CU HI N TP
137
b. f=28 Hz
d. f=0 Hz
om
.v
a. f = 28 Hz
ch
a. Bin tn hiu li ra n nh
.c
b. Tn s tn hiu li ra n nh
te
c. Bin li ra c th iu chnh c
d. Tn s li ra c th iu chnh c
.4
4. Trong mch dao ng a hi dng thch anh nh hnh 6-6, nu khng c t C1, li
ra ca thch anh c ni trc tip vi du vo ca cng NAND th hai th mch:
a. Tn s hot ng cao
b. Tnh chng nhiu cao v n hot ng nh b so snh hai ngng
c. Cng sut tiu th thp
d. L b so snh mt ngng
6. Mch c s nguyn l nh hnh sau c chc nng nh th no?
V+
a. B so snh mt ngng
b. Trig Schmitt
Vi
Opam
c. Mch dao ng a hi
Vo
V-
om
.v
d. Mch dao ng a hi i
.4
Hnh a.
te
ch
.c
+V
+V/2
-V/2
-V
+V
+V/2
-V/2
-V
Hnh c
-V/2
-V
+V
+V/2
-V/2
-V
Hnh b
+V
+V/2
-V/2
-V
Hnh d
139
a. Hnh a.
b. Hnh b.
c. Hnh c.
d. Hnh d.
8. Chc nng ca mch a hi i l g?
om
.v
ch
.c
te
.4
d. Khng c tn hiu li ra
140
Chng 7: B nh bn dn
CHNG 7: B NH BN DN
GII THIU
om
.v
.c
NI DUNG
7.1. KHI NIM CHUNG
ch
.4
te
141
Chng 7: B nh bn dn
Truy cp lin tip (serial access) hay cn gi l kiu truy cp tun t. Cc a t, bng t,
trng t, thanh ghi dchc kiu truy cp ny. Cc bit thng tin c a vo v ly ra mt cch
tun t.
7.1.2.3. Tc truy cp thng tin.
Thi gian truy cp thng tin cc b nh truy cp kiu trc tip gm thi gian tm a ch
ca nh v thi gian c/vit thng tin trn . Thi gian truy cp thng tin ph thuc ch yu
vo cng ngh ch to. Vi cng ngh MOS th thi gian truy cp khong 30 n vi trm ns.
ch
.c
B NH BN
DN
om
.v
PROM
EPROM
EEPROM
B nh c/vit
SRAM
DRAM
.4
MROM
B nh bn c
nh
te
B nh c nh
ROM
Chng 7: B nh bn dn
ngt. Do vy cc chng trnh dng cho vic khi ng PC nh BIOS thng phi np trn cc
b nh ROM.
7.1.4. T chc ca b nh
om
.v
.c
Cch t chc n gin nht l t chc theo t (word organized) vi s chn tuyn tnh. Mt
ma trn nh nh vy c di ca ct bng s lng t W v di ca hng bng s lng bit B
trong mt t. B chn t phi gii m 1 t W, ngha l gii m c mt u ra duy nht cho mt
t trong b nh. Phng php ny c thi gian truy nhp ngn nhng cn mt b gii m ln khi
tng s t ln, do lm tng gi thnh sn phm.
.4
te
ch
Kch thc ca phn gii m a ch s gim i khi t chc ma trn nh v phn logic chn
t cho php gii m hai bc. Ma trn nh s dng gii m hai bc ng vi t vt l v t logic.
T vt l bao gm s lng bit trong mt hng ca ma trn. T logic bao gm s lng bit tng
ng vi mt t logic c nhn bit v gi ra cng mt lc. Cn hai b gii m: mt b gii m
hng chn mt t vt l v mt b gii m ct gm c mt vi mch hp knh chn mt t
logic t mt t vt l chn. Mt t vt l c chia thnh S t logic. B gii m hng l b gii
m chn 1 t W m B = W/S v b chn ct cha B b hp knh mt ng t S.
V d s ROM dung lng 2048 x 8 (2048 t, mi t cha 8 bit) t chc gii m hai
bc nh hnh 7- 1.
143
Chng 7: B nh bn dn
m
vo
A0-A6
Gii m hng
1 t 128
128
Ma trn ROM
128 x 128 bit
128
4
A7-A10
8 b gii m ct
1 t 16
8
m ra
CS
om
.v
07,,,00
.c
7.2. DRAM
ch
7.2.1. Cu to ca DRAM
.4
te
Transistor
Ca
in cc
Lp
xit
n- Ngun
n- Mng
Lp
xit
Tra
Vng lu gi
in tch
bn dn loi p
WL
BL
144
BL
Chng 7: B nh bn dn
Transistor hot ng nh mt cng tc, cho php np hay phng in tch ca t khi thc
hin php c hay vit. Cc ca (Gate) ca transistor c ni vi dy hng (cn gi l dy tWL-Word Line) v cc mng (Drain) c ni vi dy ct (cn c gi l dy bit BL hoc BL Bit Line), cc ngun (Source) c ni vi t in. in p np trn t tng i nh, v th cn
s dng khuch i nhy trong mch nh. Do dng r ca transistor nn nh cn c np li
trc khi in p trn t thp hn mt ngng no . Qu trnh ny c thc hin nh mt chu
k lm ti (refresh), khi in p trn t
c xc nh ( trng thi 0 hay 1) v mc in
p logic ny c vit li vo nh.
om
.v
ch
.c
7.3. SRAM
.4
te
VCC
Tra
Tra
Tra
WL
BL
Trs Trs
WL
BL
BL
BL
Chng 7: B nh bn dn
ni vi cc ng bit v cc tn hiu c truyn ti b khuch i cui ng dy ny. V in
th chnh lch ln nn x l khuch i nh vy s nhanh hn trong DRAM (c 10 ns hoc ngn
hn), do chip SRAM cn a ch ct sm hn nu thi gian truy nhp khng c gim. Nh
vy SRAM khng cn thc hin phn knh cc a ch hng v ct. Sau khi s liu n nh, b
gii m ct chn ct ph hp v cho ra tn hiu s liu ti b m s liu ra v ti mch ra.
om
.v
Vit s liu c thc hin theo cch ngc li. Qua b m vo v b gii m ct, s liu
vit c t vo b khuch i ph hp. Cng lc b gii m hng kch hot ng dy t v
lm transistor T dn. Trig a s liu c lu tr vo cp dy bit. Tuy vy, b khuch i nhy
hn cc transistor nn n s cp cho cc ng bit mt tn hiu ph hp vi s liu vit. Do ,
trig s chuyn trng thi ph hp vi s
liu mi hoc gi gi tr c lu tr ph
thuc vo vic s liu vit trng vi s liu
lu tr hay khng.
.4
te
ch
.c
CS
WE
OE
Khng c chn
CS
Ghi
7.3. B NH C NH - ROM
Cc chip RAM khng thch hp cho cc chng trnh khi ng do cc thng tin trn b
mt khi tt ngun. Do vy phi dng n ROM, trong cc s liu cn lu tr c vit mt ln
theo cch khng bay hi nhm gi c mi.
7.3.1. MROM
146
Chng 7: B nh bn dn
ROM lp trnh theo kiu mt n c gi l
MROM. N c ch to trn mt phin silic theo
mt s bc x l nh quang khc v khch tn
to ra nhng tip gip bn dn c tnh dn in theo
mt chiu (nh diode, transistor trng). Ngi thit
k nh r chng trnh mun ghi vo ROM, thng
tin ny c s dng iu khin qu trnh lm mt
n. Hnh 7-6 l mt v d n gin v s MROM
dng diode.
Cc
dy hng (i
Cc dy bit
om
.v
ch
.c
C hai cng ngh MOS v lng cc c dng ch to MROM. Thi gian truy nhp
ca b nh lng cc khong t 50 90 ns, b nh MOS lu hn khong 10 ln. Do ROM
lng cc nhanh hn v c kh nng kch hot tt hn trong khi mch nh MOS cng dung lng
c kch thc nh hn v tiu th nng lng t hn.
7.3.2. PROM
.4
te
7.4. B NH BN C NH
7.4.1. EPROM (Erasable PROM)
Chng 7: B nh bn dn
t c kch hot th cng khng th pht ra trng u mnh vi cc ca iu khin lm
thng transistor. Lc ny ng bit khng c ni vi ngun chun v nh coi nh c gi
gi tr 0.
Ngun
Mng
Ca
hv
hv
ID
0
1
Xo
Ca iu khin
Ca ni
n- Ngun
- - - - -
Lp xit
Lp trnh
n- Mng
v0
v1
om
.v
bn dn
loi p
Lp xit
vGS
ch
.c
.4
te
148
om
.v
Chng 7: B nh bn dn
Cc chip ROM hin nay c thi gian truy nhp t 120 ns n 150 ns di hn nhiu thi gian
trong cc chip nh RAM.
7.4.3. a cng silicon- B nh FLASH
te
ch
.c
.4
149
Chng 7: B nh bn dn
VPP
Chuyn mch in th
xo
iu khin
WE
CE
OE
B nh thi
Chuyn mch in th
chng trnh
Gii
m
hng
om
.v
m
a
ch
a
ch
Ma trn t bo nh
Gii
m
ct
.c
Ca vo ra
m vo ra d liu
ch
D liu vo
.4
te
7.4.3. B nh CACHE
Vi cc my tnh c tc nhanh (trn 33MHz), cn phi xen cc trng thi i khi truy
xut d liu ti cc DRAM r tin nhng c thi gian thm nhp chm (60-120ns). iu ny lm
gim hiu sut ca my. C th gii quyt bng cch dng cc SRAM c thi gian thm nhp
ngn hn (20-25 ns, thm ch 12 ns) nhng gi thnh li rt t. B nh Cache kt hp c cc
li im nhanh ca SRAM v r ca DRAM. Gia CPU v b nh chnh bng DRAM, ngi ta
xen vo mt b nh SRAM nhanh c dung lng nh bng 1/10 hoc 1/100 ln b nh chnh gi
l cache; di s iu khin ca mch iu khin cache, b nh ny s lu tr tm thi cc s liu
thng c gi v cung cp n cho CPU trong thi gian ngn.
Cache cha cc thng tin mi va c CPU s dng gn y nht. Khi CPU c s liu n
s a ra mt a ch ti b iu khin cache. Sau mt trong hai qu trnh sau s xy ra:
150
Chng 7: B nh bn dn
-
Nh vy, cache hit t l vi truy xut thng tin c sn trong b nh cache SRAM, cn
cache miss li t l vi truy xut thng tin c trong b nh chnh l cc DRAM.
SRAM Cache
DRAM trong b
nh chnh
om
.v
CPU
B iu khin CACHE
.c
ch
.4
te
7.5.1 M rng di t
R/W
RAM
CS
RAM
R/W
CS
II
D0
BUS d liu
Dn-1
BUS d liu
151
Chng 7: B nh bn dn
R/ w c ni song song. Mt phn dung lng c tr vo mi chp. S phn chia ny da
trn c s t hp a ch vo v li vo iu khin. Hnh 7-11 l mt s v d.
A0
IC 1
A1
2k
A11
A12
A13
A0
IC 2
A1
2k
A0
IC 3
A1
2k
CS2
CS 1
A0
IC 4
A1
2k
CS3
B gii
m vo
2 ra 4
CS4
om
.v
A0
thc hin php m rng ta phi s dng mt s li vo a ch dnh ring cho b gii
m (thng l cc a ch c trng s cao). s trn ta chn 2 a ch A12 v A13 gii m.
Do ta c th nhn c 4 gi tr ra tng ng. Cc gi tr ny tc ng ln cc li vo CS
m tun t cc IC nh. Cc IC nh ny c th lm ROM hoc RAM hoc c hai l ty chn. Tun
t m cc IC theo A12, A13 nh ch ra bng hot ng sau.
A13
A12
CS
IC m
IC I
000016 - 0FFF16
IC II
100016 - 1FFF16
CS1
CS2
CS3
CS4
IC III
200016 - 2FFF16
.c
ch
te
Khong a ch
IC IV
300016 - 3FFF16
TM TT
.4
Chng 7: B nh bn dn
ngn hn (20-25 ns, thm ch 12 ns) nhng gi thnh li rt t. B nh Cache kt hp c cc
li im nhanh ca SRAM v r ca DRAM.
Trong chng ny cn gii thiu cch m rng dung lng v di t ca b nh bn dn.
CU HI N TP
Ch c th c.
b.
Ch c th vit.
c.
C th va c va vit.
d.
2. B nh RAM l b nh:
Ch c th c.
b.
Ch c th vit.
c.
C th va c va vit.
d.
.c
a.
om
.v
a.
1. B nh ROM l b nh:
Transistor.
b.
Trig.
c.
T in.
d.
Diode.
.4
te
a.
ch
b.
Trig.
a.
T in.
d.
Diode.
c.
Lng cc.
b.
MOS.
c.
Lng cc v MOS.
d.
Ch lp trnh c mt ln.
b.
Chng 7: B nh bn dn
c.
Lp trnh c v xo c.
d.
a.
b.
Transistor trng.
c.
T in.
d.
Diode.
a.
To cc nh mang gi tr 0.
b.
To cc nh mang gi tr 1.
c.
To cc nh mang gi tr 0 v 1.
d.
om
.v
b.
Lp trnh c v xo c mt ln.
c.
d.
te
ch
.c
a.
b.
c.
d.
.4
a.
b.
c.
d.
a.
154
a.
a mm.
b.
a cng.
c.
d.
om
.v
.c
ch
te
.4
khc phc nhng nhc im ca thit k bng cch s dng cc IC chc nng c nh,
cc mch tch hp chuyn bit ng dng (ASIC-Aplication Specific IC) c pht trin. Cc
ASIC c thit k p ng cc yu cu chuyn bit ca mt mch v c gii thiu bi
mt nh sn xut IC. Cc thit k ny qu phc tp khng th thc hin bng cch s dng cc IC
chc nng c nh c.
u im ca phng php ny l:
1. Gim thiu c kch thc thng qua vic s dng mc tch hp cao.
2. Gim thiu c yu cu v in.
3. Nu c sn xut theo mt quy m ln th chi ph gim ng k.
4. Vic thit k c thc thi di dng ny th hon ton khng th sao chp c.
Nhc im:
1. Chi ph pht trin ban u c th cc k ln.
155
om
.v
8. Mt tch hp cao.
ch
.c
te
PLD cng cho php nh thit k c nhiu phng tin linh ng hn th nghim vi cc
bn thit k bi v chng c th c lp trnh li trong vi giy.
.4
NI DUNG
156
8.2 SPLD
SPLD - cu kin logic kh trnh n gin. y l loi cu kin s c nhiu u im v cng
c pht trin rt mnh. V nguyn l, chng c cu to rt ging vi PROM. Vic lp trnh
cho SPLD c th c thc hin bng cc cng ngh khc nhau, da trn c s thc hin cc kt
ni bng cch s dng cu ch hoc chuyn mch. Mt SPLD, c to thnh bng mt s mng
cng AND, OR, XOR hoc c cc triger, c th thc hin nhiu hm Boole khc nhau.
PAL
u vo
PLA
om
.v
u vo
Cc SPLD u c cu to da trn mt trong hai dng cu trc chnh: mng logic kh trnh
PLA (Programmable Logic Array) v logic mng kh trnh PAL (Programmable Array Logic).
u ra
ch
.c
u ra
.4
te
Cng ngh PLD xut hin t rt sm vi cc cng ty nh Xilinx sn xut vi mch CMOS
cng sut cc thp da trn cng ngh Flash. PLD da trn cng ngh Flash cho php lp trnh v
xo vi mch nhiu ln bng in, nh tit kim c thi gian so vi xo vi mch bng tia cc
tm.
157
IO/Registers/Logic
.4
te
ch
.c
om
.v
IO/Registers/Logic
nng vo hoc ra hoc va l chn vo va l chn ra, ngoi ra cn c th thit lp cc chn I/O
ny lm vic cc mc logic khc nhau, c in tr pull-up hoc pull-down ...
Vi cu trc ng nht, gi thnh r, tnh nng kh mnh, d s dng CPLD v ang
c s dng rt rng ri trong thc t, gip cho nh sn xut pht trin nhanh sn phm ca
mnh vi gi thnh r. c bit hin nay cc hng pht trin cc h CPLD vi tnh nng rt
mnh, cng sut tiu th thp, chng ang c s dng rt nhiu pht trin cc sn phm in
t, vin thng, cng ngh thng tin, nht l trong cc thit b cm tay, di ng
om
.v
Trong thc t rt c nhiu loi CPLD khc nhau, ca cc hng khc nhau, v c pht
trin vi nhiu chng loi, th h CPLD khc nhau. Cu to, dung lng, tnh nng, c im,
ng dng ca mi loi CPLD cng rt khc nhau. Trong gio trnh ny khng i su trnh by
cu to c th ca cc h CPLD, m ch trnh by kin trc chung n gin nht ca CPLD. Khi
s dng c th loi CPLD no, ngi hc nn tham kho cc ti liu khc, nht l tham kho cc
ti liu k thut c cung cp km theo cu kin do cc hng a ra. Cc hng in t ni ting
trn th gii ang s hu, pht trin, cung cp cc loi cu kin CPLD l Xilinx, Altera
8.4. FPGA
.4
te
ch
.c
FPGA (Field Programmable Gate Array - Ma trn cng lp trnh c theo trng): c cu
trc v hot ng phc tp hn CPLD. N c th thc hin nhng chc nng phc tp u vit hn
CPLD. Nm 1985, cng ty Xilinx a ra tng hon ton mi, l kt hp thi gian hon
thnh sn phm v kh nng iu khin c ca PLD vi mt v u th v chi ph ca
GateArray. T , FPGA ra i. Hin nay, Xilinx vn l nh sn xut chip FPGA s mt trn th
gii.
Cu trc FPGA n gin gm cc t bo logic (Logic Cell), cc khi cch u nhau, lin kt
nh cc ng kt ni c th thay i c theo yu cu ca ngi thit k. Ngha l ngi thit
k c quyn thit k, lp trnh v thay i mch in. Hin nay, FPGA c mt kh cao, ln ti
hng trm t cng v cu trc cng a dng, phc tp hn. Nhiu chc nng phc tp c tch
hp sn tng hiu qu s dng FPGA. V d nh ngoi nhng khi t bo logic, nhiu h
FPGA c tch hp thm cc khi chc nng nh cc b nhn cng, khi nh, PLL, thm ch
c mt b vi x l mnh
C hai loi FPGA c bn: loi lp trnh li c, da trn cng ngh SRAM v loi lp
trnh mt ln.
159
SRAM xc nh cc kt ni
Kt ni dng b cu ch
om
.v
nh iu
khin b chn
knh
u ra
u vo
nh iu
khin im
kt ni
te
ch
.c
Bng LUT 4 u vo
.4
im kt ni
Hai dng ny khc nhau v quy trnh thc hin t bo logic v c ch c s dng to
kt ni trong thit b.
FPGA
- Cu trc da vo LUT
- Mng kt ni trung tm
- Mt tch hp cao
- Cu trc ng nht
om
.v
ch
.c
te
.4
Trong thc t c rt nhiu hng in t trn th gii cung cp cc sn phm PLD v b cng
c phn mm thit k i km. Mi h CPLD, FPGA ca cc hng c nhng quy trnh thit k
khc nhau dnh cho chng, tuy nhin v c bn chng vn c quy trnh thit k chung nht inh.
Khng mt tnh tng qut, ngi hc tip cn d dng hn, trong ti liu ny vic trnh by quy
trnh thit k cho CPLD/FPGA c ly v d, c th ho cho CPLD/FPGA ca hng Xilinx
Mt hng cung cp cc sn phm PLD s 1 th gii hin nay s dng b cng c phn mm
thit k ISE.
S lng chn vo/ra: phi xc nh vi mch thit k cn bao nhiu u vo, bao nhiu u
ra.
161
om
.v
.c
te
ch
+ MultiLINX : Cp np da trn giao chun giao tip ni tip USB hoc RS232, cp np
ny c tc truyn trong di rng v giao din c in p iu chnh c ph hp vi vic
giao tip vi cc h thng v cc chn I/O hot ng cc mc in p khc nhau 5V; 3,3V;
2,5V. V c thit k h tr cho cc phn mm g ri phn cng trc kia, nay chng
tr ln li thi khi c s ra i ca cng c g ri phn cng ChipScope ILA.
.4
+ Parallel Cable IV: Cp np s dng cng giao tip song song ca my tnh, c pht
trin thay th cho chun cp np Parallel Cable III v cho php tng tc ln hn 10 ln v
h tr cho tt cc cc vi mch s dng mc in p I/O t 5V xung 1,5V. Hin nay chun cp
np ny c dng ph bin hn c.
Lp trnh bn ngoi
162
dng cng c 3rd part boundary scan, cc gii php phn mm km theo, cp ISP, thit b kim tra
t ng ATE v h tr lp trnh cng nh cc thit b lu tr cu hnh.
om
.v
Gii php cu hnh hin i nht l nhm cu hnh System ACE. Vi gii php System
ACE, ngi thit k c th d dng s dng giao din vi x l trong System ACE trc tip phi
hp cu hnh FPGA theo cc yu cu ca h thng. Gii php u tin trong nhm ny l System
ACE CF, cung cp cng ngh iu khin a Microdrive kch thc mt inch v CompactFlash
cng nh b lu tr cu hnh c dung lng 8 gigabits. Ngoi ra, System ACE CF cng c
thit k trc, cung cp cc c tnh hin i tn dng kh nng cu hnh li linh hot ca
FPGA, bao gm:
.c
- M ha
ch
te
.4
- linh hot: Vi System ACE CF, c th s dng mt thit k cho nhiu ng dng khc
nhau, nh gim ng k thi gian hon thnh sn phm. Thay v thit k vi bo mch tng t
nhau ph hp vi cc chun khc nhau, gi y ngi thit k ch phi thit k mt bo mch duy
nht vi nhiu cu hnh c lu tr trong b nh System ACE CF. Mi bo c th chn cc cu
hnh ph hp vi cc chun khc nhau bng cch khi to gi tr mc nh tng ng c lu
trong b nh ACE. H thng cn cho php lu nhiu cu hnh cho mt thit k trong mt System
ACE CF n. V d nh trong qu trnh thit k mu, ngi thit k c th lu cc cu hnh hot
ng, cu hnh kim tra v cu hnh g ri trong b nh ACE, ng thi c th chn cc cu hnh
khc chy th bn thit k ca mnh.
163
om
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.c
Xilinx cung cp cc cng c thit k in t hon chnh, cho php thc hin thit k trn
cc thit b logic kh trnh ca Xilinx. Cc cng c ny kt hp cng ngh tin tin vi giao din
ha linh hot, d s dng ngi thit k c c thit k ti u. B cng c phn mm hin
ang c s dng rng ri l ISE vi phin bn mi nht l 7.0 (nm 2005).
ch
Xilink cng cung cp ISE di dng cc gi phn mm c cu hnh khc nhau vi gi thnh
khc nhau:
+ ISE WebPACK - bn min ph c th dng thit k cho tt c cc h CPLD ca Xilinx
te
.4
Virtex-4, FPGA LX15, LX25, SX25, FX12, Spartan-3 FPGA ln n 1500 ngn cng v
tt c cc h CPLD.
+ Gi phn mm Foundation: c th thit k cho tt c cc loi FPGA v CPLD ca Xilinx
Qu trnh thit k cho CPLD ch yu l thc hin trn cc cng c phn mm, lu thit
k chung cho CPLD (V d s dng phn mm ISE) nh hnh v sau, bao gm cc bc nh sau:
+ Nhp thit k (Design Entry):
y l bc u tin v quan trng nht ca qu trnh thit k cho CPLD. Cc cng c thit
k cho php nhp thit k cho php nhp thit k theo cc cch sau:
- Nhp thit k theo s nguyn l Schematic, ngi thit k s dng cc modul c sn
trong th vin Schematic ghp ni chng vi nhau to thnh bn thit k theo yu cu, cch
ny c th thc hin thit k nhanh nhng s rt kh khn v khng ti u ti nguyn ca CPLD
164
khi thit k phc tp, v thit k khng th s dng sang cng c thit k CPLD ca cc hng
khc. T s nguyn l thit k c cng c phn mm s chuyn i sang file ngn ng m
t phn cng HDL, m ph bin l VHDL hoc Verilog.
- Nhp thit k s dng ngn ng m t phn cng HDL (VHDL, Verilog, ABEL,
AHDL...), Ngi thit k c th s dng chng trnh son tho thc hin vic m t ton b
bn thit k ca mnh di dng ngn ng HDL no m cng c thit k c th tng hp c.
C rt nhiu phng php m t, mc tru tng khc nhau khi thit k, mi cch m t khc
nhau c th to ra mt cu trc mch khc nhau trong CPLD mc d chng c cng chc nng.
HDL
Verilog/VHDLL
State Machines
StateCad
om
.v
Schematic
ECS
Design Entry
Design Verification
ch
.c
Functional Simulation
ModelSim XE
Design Synthesis
.4
te
Design Implementation
Translate
Map
Timing Simulation
Static Timing Analysis (ECS)
ModelSim XE
Configuration
Download (iMPACTE)
165
Do ngi thit k cn thc hin phn tch bi ton, tm hiu ti nguyn, cu trc ca
CPLD, yu cu v thi gian thit k s dng kiu m t. Mc tru tng trong khi m t
ph hp va m bo yu cu v thi gian thit k va ti u c vic s dng ti nguyn ca
CPLD.
- Nhp thit k di dng s : Cng c thit k cn cho php nhp thit k vo di dng
s m in hnh l hnh trng thi, sau chng cng c chuyn i sang HDL.
om
.v
Vic nhp thit k rt linh hot, c th s dng c 3 cch trn thc hin cc phn khc
nhau ca thit k.
+ Kim tra, m phng thit k (Design Verification): Thc hin kim tra, m phng chc
nng hot ng ca thit k HDL to ra trn. Cc cng c thit k u h tr vic m phng
chc nng hot ng ca bn thit k HDL theo m hnh hot ng (Behavioral Model), mc
m phng ny c lp vi loi CPLD c la chn. Bc ny c th khng cn phi thc
hin trong khi thit k.
ch
.c
+ Tng hp thit k (Design Synthesis): Sau khi hon thnh m phng thit k, bc tng
hp tip theo c nhim v chuyn thit k di dng file vn bn HDL thnh dng file netlist,
thc hin m t mch thc mc thp di dng cng logic v kt ni gia chng vi nhau. C
th s dng cc cng c tng hp ca cc hng khc nhau.
.4
te
Mi cng c c th to ra file netlist theo nh dng ring (v d ca XST ca Xilinx XNFXilinx Netlist Format) nhng c th t la chn to ra file netlist di dng nh dng chun
EDIF (Electronic Digital Interchange Format) m tt c cc cng c c th hiu c.
U1A
U1A
U3A
U2A
U2A
U3A
Chn cc cng
A
B
U4A
U1A
Thc hin kt ni
U4C
U4B
U2A
U3A
U4D
Component AND G1
Component OR G
Component NOT G3
Net N1: A. G1:a. G3:a
Net N2: B. G1:b. G2:a
Net N3: G1:c. P
Net N4: G3:b. G2:b
Net N5: G2:c. Q ;
Ghp cc b m v/ra
To Netlist
166
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+ Translate (bin dch): Bc ny nhm thc hin kim tra thit k v m bo netlist ph
hp vi kin trc chn, kim tra file rng buc "constraints File" ca ngi s dng pht
hin cc li mu thun vi tham s ca chip chn. Bin dch thng bao gm cc qu trnh: ti
u ho, bin dch thnh cc thnh phn vt l ca thit b; kim tra rng buc thit k. Khi kt
thc bc bin dch, s c mt bn bo co v cc chng trnh c s dng, danh sch cc cng
I/O v cc thit b c s dng trong thit k, nh ngi thit k s la chn c phng n
thit k ti u.
te
ch
.c
.4
Place and Route l qu trnh phc tp, do n chim thi gian nhiu nht. Tuy nhin,
bc ny ch c th hot ng tt nu chip chn p ng cc tuyn lin kt cho thit k.
Nu khng, ngi thit k s phi chn chip c dung lng ln hn. Sau bc ny to ra c file
cu hnh *.jed c th c np vo cho CPLD.
+ Timing Simulation (M phng c tham s thi gian): Sau bc Place and Route ngi
thit k c th thc hin m phng thit k mc cng logic c nh v tr v nh tuyn
trn CPLD, phn mm s dng file cu hnh c to ra v kt hp vi th vin v m hnh
thi gian ca cc h CPLD (V d ISE ca Xilinx th dng th vin VITAL), thc hin m
phng hot ng ca thit k m c tnh n cc tham s thi gian tr, thi gian thit lp ca
cc cng logic trong CPLD. Bc ny rt quan trng vi nhng thit k phc tp, tc ln.
167
ch
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Configuration
.4
te
Download (iMPACTE)
TM TT
168
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Trong ton b lu thit k cho CPLD hoc FPGA, bc nhp thit k l bc quan trng
v tn nhiu cng sc nht, n quyt nh phn ln n kt qu ca cng vic thit k. Cc cng
c thit k h tr nhiu phng php nhp thit k khc nhau, tuy nhin phng php nhp thit
k dng ngn ng m t phn cng HDL l u vit hn c v c s dng ch yu trong qu
trnh thit k s ni chung v thit k cho CPLD/FPGA ni ring. Hin nay c nhiu ngn ng
HDL c s dng, tuy nhin trong phn ny ch gii thiu phng php thit k dng ngn ng
VHDL v gii thiu nhng c im ca VHDL khin n c tr thnh mt ngn ng HDL
ang c ging dy v s dng nhiu trng i hc trn th gii.
.4
te
ch
.c
Ngy nay, cc mch tch hp ngy cng thc hin c nhiu chc nng, do , vn thit
k mch cng tr nn phc tp. Nhng phng php truyn thng nh dng phng php ti
thiu ho hm Boolean hay dng s cc phn t khng cn p ng c cc yu cu t ra
khi thit k. Nhc im ln nht ca cc phng php ny l chng ch m t c h thng
di dng mng ni cc phn t vi nhau. Ngi thit k cn phi i qua hai bc thc hin hon
ton th cng: l chuyn t cc yu cu v chc nng ca h thng sang biu din theo dng
hm Boolean, sau cc bc ti thiu ho hm ny ta li phi chuyn t hm Boolean sang s
mch ca h thng. Cng tng t khi phn tch mt h thng ngi phn tch cn phi phn tch
s mch ca h thng, ri chuyn n thnh cc hm Boolean, sau mi lp li cc chc nng,
hot ng ca h thng. Tt c cc bc ni trn hon ton phi thc hin th cng khng c bt
k s tr gip no ca my tnh. Ngi thit k ch c th s dng my tnh lm cng c h tr
trong vic v s mch ca h thng v chuyn t s mch sang cng c tng hp mch vt
l dng cng c Synthesis. Mt nhc im khc na ca phng php thit k truyn thng l s
gii hn v phc tp ca h thng c thit k. Phng php dng hm Boolean ch c th
dng thit k h thng ln nht biu din bi vi trm hm. Cn phng php da trn s
ch c th dng thit k h thng ln nht cha khong vi nghn phn t.
NI DUNG
9.1. GII THIU NGN NG M T PHN CNG VHDL
.c
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VHDL l ngn ng m t phn cng cho cc mch tch hp tc rt cao, l mt loi ngn
ng m t phn cng c pht trin dng cho trng trnh VHSIC( Very High Speed Itergrated
Circuit) ca b quc phng M. Mc tiu ca vic pht trin VHDL l c c mt ngn ng m
phng phn cng tiu chun v thng nht cho php th nghim cc h thng s nhanh hn cng
nh cho php d dng a cc h thng vo ng dng trong thc t. Ngn ng VHDL c ba
cng ty Intermetics, IBM v Texas Instruments bt u nghin cu pht trin vo thng 7 nm
1983. Phin bn u tin c cng b vo thng 8-1985. Sau VHDL c xut t chc
IEEE xem xt thnh mt tiu chun chung. Nm 1987 a ra tiu chun v VHDL( tiu chun
IEEE-1076-1987).
te
ch
VHDL c pht trin gii quyt cc kh khn trong vic pht trin, thay i v lp ti
liu cho cc h thng s. Nh ta bit, mt h thng s c rt nhiu ti liu m t. c th vn
hnh bo tr sa cha mt h thng ta cn tm hiu k lng ti liu . Vi mt ngn ng m
phng phn cng tt vic xem xt cc ti liu m t tr nn d dng hn v b ti liu c th
c thc thi m phng hot ng ca h thng. Nh th ta c th xem xt ton b cc phn t
ca h thng hot ng trong mt m hnh thng nht.
.4
170
om
.v
ch
.c
VHDL l ngn ng cho php m t cc thit b phn cng s tru tng, n khng da vo
cng ngh thit b phn cng s, phng php c s dng thit k thit b s, m nhng khi
nim, m hnh tru tng ca thit b phn cng s c a ra nh l nn tng ca ngn ng. Do
dng VHDL cho php m t c hu ht cc h thng phn cng s. Cc m hnh tru tng
gm:
M hnh hot ng (a Model of Behavior).
.4
te
171
Trong ngn ng VHDL gm c 3 i tng l: tn hiu - signal, bin - variable, hng constant, mi i tng c khai bo da vo t kha tng ng v chng c mc ch s dng
nh sau:
+ Tn hiu Signal: l i tng biu din ng kt ni cc gia cc cng vo/ra ca
thc th, gia cc cng vo/ra ca cc khi thnh phn phn cng xut hin trong thc th
Chng l phng tin truyn d liu ng gia cc thnh phn ca thc th.
om
.v
Tn hiu c tnh ton cc rt cao, chng c th c khai bo trong package (tn hiu ton
cc, c s dng bi mt s thc th), khai bo trong thc th - Entity (tn hiu ni b dng
trong thc th, c th c tham chiu bi bt k kin trc no ca thc th ), khai bo trong
kin trc Architecture (tn hiu ni b dng trong kin trc, c th c s dng trong bt c
cu trc lnh no trong kin trc). Cc tn hiu c th c s dng nhng khng c khai bo
trong tin trnh process, trong chng trnh con. V tin trnh v chng trnh con l thnh phn
c s ca m hnh v chng c coi nh cc hp en. C php khai bo tn hiu nh sau:
Signal tn_tn_hiu {,tn_tn_hiu}:kiu_d_liu [:=gi_tr_khi_to];
V d: Signal a,b,c: Bit:=1;
.c
ch
te
V d: variable x : Bit:=1;
.4
172
Cc i tng khi khai bo phi c xc nh kiu d liu tng ng. VDHL nh ngha
nhiu kiu d liu khc nhau ph hp vi vic m t, thit k, m phng cc h thng s khc
nhau trong thc t.
9.2.2 Kiu d liu trong VHDL
Kiu ghp: cc d liu di dng mt nhm cc thnh phn nh mng, bng ghi
(record). Bit_logic_vector, std_logic_vector v String u l nhng dng d liu ghp
c nh ngha sn.
VHDL Subtypes: dng d liu con do ngi dng t nh ngha da trn nhng dng
c sn.
ch
.c
om
.v
te
Cc kiu d liu c nh ngha trong gi Standard cha trong th vin chun Standard
Library ca VHDL l: bit, boolean, integer, real, physical, character, std_logic and std_ulogic,
Bit_logic_vector, std_logic_vector v String v mt s kiu d liu con. C php chung nh
ngha kiu d liu nh sau:
.4
a. Kiu v hng
P : PROBABILITY := 0.5 ;
om
.v
.c
units
.4
type
te
ch
fs; -- n v c bn
ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
V d s dng:
ms = 1000 us;
End Units;
174
type
std_ulogic
( U,
X,
is
type
-- Uninitialize
std_logic
( U,
-- Forcing Unknown
X,
is
-- Uninitialize
-- Forcing Unknown
--
Forcing Zero
0,
--
Forcing Zero
1,
--
Forcing One
1,
--
Forcing One
Z,
--
High Impedance
Z,
--
High Impedance
W,
-- Weak Unknown
W,
-- Weak Unknown
L,
--
Weak Zero
L,
--
Weak Zero
H,
--
Weak One
H,
--
Weak One
--
Dont Care
--
Dont Care
) ;
) ;
0,
om
.v
Hai kiu d liu std_logic v std_ulogic tng t nhau, chng ch khc nhau ch l kiu
std_ulogic khng c hm phn di (unresolved) hm quyt nh gi tr tn hiu, do s c li
khi cc tn hiu kiu std_ulogic c ni chung vo 1 im. Th vin cng cung cp hm pht
hin li ny ca cc tn hiu kiu std_ulogic.
A,B,C,Res_Out : std_logic ;
signal
Out_1 : std_ulogic ;
ch
Out_1 <= A ;
.c
signal
Out_1 <= B ;
Out_1 <= C ;
te
Out_1
.4
Res_Out <= B;
Res_Out <= C;
B
C
Res_Out
Thc hin c
C li
Res_Out <= A;
(K hiu <= dng trn l lnh gn tn hiu, lnh gn tn hiu thc hin c vi 2 d liu
cng kiu, cng ln, gi tr ca tn hiu bn phi s c gn cho tn hiu bn tri).
- Kiu d liu lit k t nh ngha: Kiu d liu lit k, do ngi s dng t nh ngha,
cho php m t rt sng sa, v linh hot cho cc m hnh phn cng s vi mc tru tng
cao. Kiu d liu ny dng nhiu m t hnh trng thi, cc h thng phc tp
Tng t cc ngn ng lp trnh, VHDL cng c cc kiu d liu ghp l nhm cc phn t
d liu theo dng mng (array) hoc bng ghi (record).
+ Mng Array:
175
om
.v
.c
State2;
.4
te
ch
- Php gn cho mng: 2 mng phi cng kiu, cng ln, php gn s thc hin gn theo
tng phn t theo th t t tri sang phi:
My_BusA
My_BusA
My_BusB
My_BusB
Cch biu din s liu bit_vector v std_logic_vector: B|O|X gi_tr (dng du nhy kp).
Trong B : Binary -Kiu nh phn, O: Octal - kiu bt phn, X: hexadecimal.
X1AF=B0001_1010_1111= B000_110_101_111=O0657
- Php gp ( ): cho php nhm c d liu v hng v d liu mng thun tin cho cc
php gn cho mng:
176
: std_logic;
WORD <= ( A, B, C, D ) ;
H_Byte <= (7|6|0=>1, 2 to 5 => 0 );
om
.v
.c
Bng ghi l nhm nhiu phn t c kiu d liu khc nhau thnh i tng duy nht.
Mi phn t ca bn ghi c truy nhp ti theo tn trng.
ch
te
.4
PARITY
ADDRESS : std_logic_vector ( 0 to 3 );
end record ;
. . .
signal
PARITY
TX_PACKET, RX_PACKET
ADDRESS
: OPCODE;
DATA BYTE
177
Mng 2 chiu l kiu d liu mng ca cc phn t mng mt chiu hay bng ghi. Mt s v
d nh ngha v khai bo kiu d liu mng 2 chiu nh sau:
type Mem_Array is array (0 to 3) of std_logic_vector (7 downto 0);
type
Data_Array is array ( 0 to 2 ) of
OPCODE ;
...
signal My_Data:Data_Array ;
om
.v
signal My_Mem:Mem_Array ;
3 => 11110000);
.c
ch
te
V d:
.4
Ton t logic: c s dng cho cc dng d liu l bit, boolean, bit_vector v std_logic_vector.
Ton t logic gm c: and, or, nand, nor, xor, not, xnor.
A
B
F
Z
V d: Z <= A and B;
178
H
Y
G
Y <= G or ( F and H ) ;
signal
A_vec,
B_vec,
C_vec :
bit_vector(7 downto 0 ) ;
...
C_vec <= A_vec
and
B_vec ;
A_vec (7)
B_vec (7)
C_vec (7)
A_vec (6)
B_vec (6)
C_vec (6)
A_vec (5)
B_vec (5)
C_vec (5)
.
.
.
C_vec (0)
om
.v
+ Php ton logic thc hin vi tng phn t ca mng v A_vec (0)
theo th t t tri sang phi.
B_vec (0)
FLAG_BIT : boolean ;
signal
A, B : integer ;
.c
V d:
ch
te
+ Mng c di khc nhau th php quan h thc hin u tin phn t t tri sang phi v
so snh theo gi tr ASCII.
A_vec : bit_vector
( 7 downto 0 ) := 11000110 ;
B_vec : bit_vector
( 5 downto 0 ) := 111001 ;
.4
signal
signal
...
if ( A_vec
> B_vec )
State <=
then
Normal;
else
Code_Red;
State <=
end if;
179
2;
D_vec =00011000
2;
D_vec =11110001
3;
D_vec =11011000
2;
D_vec =00110001
D_vec =00011000
om
.v
Ton t ghp ni: ton t & cho php ghp ni mt cch linh hot cc d liu n v d liu
dng mng thnh cc mng ln hn.
Ton t tch: cho php ta ly ra mt s thnh phn ca mng, chiu ch s ca php tch phi
cng chiu nh ch s nh ngha cho mng.
signal
.c
V d: signal
ch
Ton t thuc tnh: Xc nh thuc tnh d liu ca i tng bin v tn hiu. C php
chung:
te
i_tngthuc_tnh
- Cc thuc tnh c nh ngha trc cho kiu d liu mng trong VHDL l:
.4
+ left, right: tr li ch s ca phn t bn tri nht hoc bn phi nht ca d liu mng.
+ high, low : tr li ch s ca phn t cao nht hoc thp nht ca kiu d liu mng.
180
Entity: (Thc th) - cho php khai bo cc giao din ca mt khi thit k s no
: nh khai bo cc chn vo/ra, cc tham s ca khi mch...
om
.v
te
ch
.c
.4
Khai bo thc th trong VHDL phn nh ngha cc ch tiu pha ngoi ca mt phn t hay
mt h thng. Thc cht ca vic khai bo thc th chnh l khai bo giao din ca h thng vi
bn ngoi. Ta c th c tt c cc thng tin kt ni mch vo mch khc hot thit k tc nhn
u vo phc v cho mc ch th nghim. Tuy nhin hot ng tht s ca mch khng nm
phn khai bo ny. C php khai bo chung ca mt Entity nh sau:
entity Tn_thc_th is
generic(--Khai bo danh sch cc tham s generic
Tn_tham_s : [Kiu_d_liu] [:=gi_tr_khi_to];
...
);
port(-- Khai bo danh sch i tng cc port vo ra
Tn_cng : [mode] [Kiu_d_liu] [:=gi_tr_khi_to];
...
);
end Tn_thc_th;
181
om
.v
+ [mode]: ch hng tn hiu ca cng c th l: (in, out, inout hoc buffer). Trong
cng dng in ch dng c d liu. Cng dng out ch dng gn gi tr d liu. Cng inout
cho php ng thi va c va gn gi tr d liu trong v ngoi chng trnh. Cng dng
buffer cho php c 2 thao tc c v gn d liu t bn trong chng trnh, nhng ch cho php
c d liu t ngoi chng trnh.
V d khai bo thc th cho mt cng logic AND:
PLD
Logic_AND
ch
.c
entity Logic_AND is
port(A, B : in std_logic ;
Y
: out std_logic) ;
end Logic_AND;
te
.4
End Tn_kin_trc;
Phn khai bo kin trc c th bao gm cc khai bo v cc i tng signal, constant, kiu
d liu, khai bo cc phn t bn trong h thng (component), hay cc hm (function) v th tc
(proceduce) s dng m t hot ng ca h thng. Tn ca kin trc l nhn c t tu theo
ngi s dng
VHDL cho php to ra nhiu m t Architecture cho mt thc th, cho php thc hin
nhiu cch m t hot khc nhau cho mt thc th. Mi cch m t hot ng s ti u v mt
thi gian thit k hay tin cy hay ti u v ti nguyn s dng khi tng hp
C 3 cch chnh m t kin trc ca mt phn t (hoc h thng s) l m hnh hot
ng (Behaviour), m t theo m hnh cu trc logic (Structure), v m hnh lung d liu. Tuy
nhin m t cho mt h thng, trong mt kin trc c th kt hp s dng 2 hoc c 3 m hnh
m t trn thc hin cho tng thnh phn con tng ng ca h thng s. Trong phn sau ca
ti liu ny s trnh by chi tit hn cc phng php m t ny.
182
entity Half_Add is
. . .
end Half_Add;
architecture
BEH of
Half_Add
is
-- Kin trc m t
theo m hnh hot ng
RTL of
Half_Add
is
-- Kin trc m t
theo m hnh lung d
liu
XLX of
Half_Add
. . .
end
BEH ;
architecture
RTL ;
architecture
om
.v
end
. . .
. . .
end XLX ;
+ Package v Package Body
is
-- Kin trc m t
theo m hnh cu trc
logic
ch
.c
.4
te
183
package My_Pack is
constant. . .
. . .
function bv_to_integer (BV: bit_v..
return integer
. . .
component . . .
. . .
subtype. . .
use work.My_Pack.all;
entity . . .
om
.v
te
ch
end function;
. . .
end My_Pack ;
.c
.4
Phn tch VHDL l mt qu trnh kim tra cc n v thit k VHDL cho ng c php
v ng ngha, cc n v thit k VHDL c lu vo th vin s dng sau ny. Th vin thit
k cha cc nhng phn t th vin sau:
Package: cha nhng m t khai bo c dng chung.
Entity: l nhng m t giao din thit k c dng chung.
w
-
184
library My_Lib ;
use My_Lib.Fast_Counters.all ;
entity Mod1 is
port ( . . .
om
.v
.c
ch
for c_t_ca_khi
{mnh__use}
{cc_phn_t_ca_cu_hnh}
te
end for;
.4
V d:
use work.all;
for structure_view
for
use
end
for
use
end
for
end
end
end
a1:alu
configuration ttl.sn74ls181;
for;
m1,m2,m3: mux
entity multiplex4 (behavior);
for;
all: latch -- use defaults
for;
for;
configuration v4_27_87;
185
CPLD/FPGA
entity
architecture
process
Variables
Signals
Input Ports
om
.v
Output Ports
.c
ch
te
.4
-- Khai bo thc th
Entity Tn_thc_th is
End Tn_thc_th;
-- Bt u vit
186
...
{ Vit cc m t dng cu trc lnh song song hay process khc }
...
End Tn_kin_trc;
om
.v
Mt trong cc nhim v rt quan trng l kim tra bn m t thit k. Kim tra mt m hnh
VHDL c thc hin bng cch quan st hot ng ca n trong khi m phng v cc gi tr thu
c c th em so snh vi yu cu thit k.
.c
Mi trng kim tra c th hiu nh mt mch kim tra o. Mi trng kim tra sinh ra cc
tc ng ln bn thit k v cho php quan st hoc so snh kt qu hot ng ca bn m t thit
k. Thng thng th cc bn m t u cung cp chng trnh th. Nhng ta cng c th t xy
dng chng trnh th (testbench). Mch th thc cht l s kt hp ca tng hp nhiu thnh
phn. N gm ba thnh phn. M hnh VHDL qua kim tra, ngun d liu v b quan st. Hot
ng ca m hnh VHDL c kch thch bi cc ngun d liu v kim tra tnh ng n thng
qua b quan st. Hnh 9-2 l s tng qut ca mt chng trnh th (Testbench).
te
ch
.4
Testbench Entity
DUT
Observer
Data
Source
(stimuli
Generator
Generics
187
;
A
M t to
kch thch
DUT
Logic_AND
Quan st
om
.v
ch
ENTITY Test_bench IS
.c
USE ieee.std_logic_1164.ALL;
END Test_bench;
te
.4
A : IN std_logic;
B : IN std_logic;
Y : OUT std_logic
);
END COMPONENT;
std_logic:='0';
SIGNAL B :
std_logic:='0';
SIGNAL Y :
std_logic;
SIGNAL A :
BEGIN
188
END;
Trong cc phn mm thit k sau khi hon thnh cc m t cho Test_bench, ngi thit k
s chy cng c m phng, cc tn hiu u ra ca DUT s c mc tnh c ra v cho php
ngi thit k quan st d dng di dng gin thi gian, hay cc file s liu
om
.v
+ Cu trc process.
ch
.c
te
+ Khi.
.4
a. Cu trc Process:
Process trong mt thit k c thc hin song song. Tuy nhin, ti mt thi im xc nh
ch c mt cu lnh tun t c thc hin trong mi cu trc Process. Cu trc tng qut:
Trong cc phn t trong du [ ] c th c hoc khng.
189
entity Logic_AND is
Port ( A,B : in std_logic;
: out std_logic);
.c
om
.v
end Logic_AND;
ch
te
Process(A,B)
C<= A and B;
.4
end Process;
end Behavioral;
190
Process 1
A
B
G1
C<=A and B
...
G2
Process 2
If C = 1
then
...
C
C
Process 3
G3
C<=A and B
...
Process n1
Sig1
om
.v
Process n
process (C,..)
begin
If C = 1
then
...
C
C
Process n4
Sig2
Process n2
process n
process (...
Rst
ch
.c
process (C,..)
begin
Process n3
te
.4
Php gn tn hiu song song s dng bn trong cc Architecture nhng bn ngoi Process.
Dng n gin nht ca php gn tn hiu song song c c php nh sau:
...
191
.c
end Behavioral;
om
.v
end process;
begin
ch
Php gn tn hiu c iu kin l cu trc lch song song thc hin php gn gi tr ca cc
biu thc cho mt tn hiu ch ty theo cc iu kin t ra. C php chung:
te
.4
<biu_thc>[after <biu_thc_thi_gian>];
Cu trc php gn tn hiu c iu kin c th coi l cu trc song song ca lnh tun t If
c thay th tng ng vi Process cha lnh tun t if.
architecture ...
begin
Z <= A when Sel=00 else
B when Sel=10 else
C when Sel=11 else
X ;
end architecture;
192
architecture ...
begin
process(A,B,C, SEL )
begin
case (SEL) is
when 00 =>Z <= A;
when 10 =>Z <= B;
when 11 =>Z <= C;
when others =>Z<= X;
end case;
end process;
architecture ...
begin
process (A,B,C, SEL)
begin
case SEL is
when 00 => Z <= A
when 10 => Z <= B
when 11 => Z <= C
when others => Z <=
end case;
end process;
end architecture;
;
;
;
X;
te
ch
architecture...
with SEL select
Z<= A when 00,
B when 10,
C when 11 ,
X when others ;
end Cc
architecture;
9.2.7
cu trc lnh tun t
.c
om
.v
when others;
e. Khi (Block)
.4
Block bao gm tp hp cc cu trc lnh song song. Mt kin trc c th phn tch thnh
mt s c cu trc logic. Mi khi biu din mt thnh phn ca m hnh v thng c s dng
t chc mt tp hp cc cu trc song song phn cp. C php chung:
<nhn>: Block
{<phn_khai_bo>}
begin
{<cu_lnh_song_song>} c trnh t bt k
end block;
Khai bo b danh.
Khai bo component.
Lut use.
193
Php gi chng trnh con song song tng ng vi cc process bao gm cc php gi
chng trnh con tun t tng ng. Mi php gi chng trnh con tng ng vi mt process
khng cha dy danh sch cc tn hiu kch thch, phn khai bo rng v phn thn cha mt php
gi chng trnh con, tip theo l mt cu lnh wait.
9.2.8 Cu trc lnh tun t
om
.v
Cu lnh if.
Cu lnh case.
Cc lnh lp.
te
ch
.c
a. Php gn bin
bin := biu_thc
.4
process( Clk )
variable
B, C, D : bit := 1 ;
begin
If (Clkevent and Clk =1) then
B := A ;
C := B ;
D := C ;
end if ;
end process ;...
194
Clk
...
process( Clk )
variable
B, C, D : bit := 1;
begin
If ( Clkevent and Clk =1 ) then
D := C;
A
C := B;
B := A;
end if;
end process ;
Clk
om
.v
.c
ch
Khc vi php gn bin, php gn tn hiu trong Process khng c cp nhp ngay tc th
m php gn ch c t k hoch thc hin v kt qu ch c cp nhp sau khi kt thc
Process.
te
V d:
.4
signal Clk, A, B, C, D
bit := 1;
process( Clk )
begin
If (Clkevent and Clk =1) then
A
B <= A ;
C <= B ;
D <= C ;
Clk
end if ;
end process ;
End Behavior;
c. Lnh if
Lnh ny cho php cc php ton c thc hin trn mt iu kin no . C ba dng c
bn l:
+ Dng 1:
if (iu_kin) then
<Cc_cu_lnh_tun_t>;
end if;
+ Dng 2:
195
(iu_kin_2) then
(iu_kin_3) then
<Cc_cu_lnh_tun_t>;
else
<Cc_cu_lnh_tun_t>;
end if;
om
.v
elsif
<Cc_cu_lnh_tun_t>;
.c
ch
begin
If
00)
then
10)
then
11)
then
01)
A
B
then
.4
(Sel =
Z <= A ;
elsif (Sel =
Z <= B ;
elsif (Sel =
Z <= C ;
elsif (Sel =
Z <= D ;
end if;
end process ;
te
C
D
Sel
d. Lnh case:
Lnh case c s dng trong trng hp c mt biu thc kim sot nhiu r nhnh
trong chng trnh VHDL. Cc lnh tng ng vi mt trong cc la chn s c thc hiu nu
biu thc kim sot c gi tr bng gi tr tng ng ca la chn . C hai dng c bn:
Dng 1:
Case (biu_thc_kim_sot) is
When <gi_tr_la_chn> =>
<Cc_cu_lnh_tun_t>;
When <gi_tr_la_chn> =>
196
...
When others =>
om
.v
<Cc_cu_lnh_tun_t>;
end case;
(A, B, C, D, Sel )
=>
=>
=>
=>
Z
Z
Z
Z
<=
<=
<=
<=
A
B
C
D
;
;
;
;
.4
te
case Sel is
when 00
when 01
when 10
when 11
ch
process
begin
.c
V d:
end case ;
end process ;
A
B
C
D
Sel
Null;
Trong VDHL khi chng trnh m phng gp cu lnh Null n s b qua lnh ny v thc
hin lnh tip theo sau. Thng thng lnh Null dng ch trng hp khng thc hin ca lnh
mt cch tng minh khi c cc iu kin tr li gi tr true. Do lnh Null thng c dng
trong cc cu lnh case i vi nhng gi tr la chn khng cn thao tc. V d:
197
process
begin
(A, B, C, D, Sel )
case Sel is
when 00 =>
Z <= A ;
when 01 =>
Z <= B ;
when 10 =>
Z <= C ;
when others => Null;
B
C
end case ;
end process ;
Sel
om
.v
f. Cc lnh lp
Lnh lp loop cha thn vng lp bao gm dy cc cu lnh s c thc hin khng hoc
nhiu ln. C php ca lnh lp nh sau:
[<nhn>:] [<s__lp>] loop
{<lnh_tun_t>}|
{next [<nhn>] [when <iu_kin>];}|
.c
ch
- <nhn>: nhn ca vng lp v thng c dng xy dng nhng vng lp lng nhau,
trong mi vng lp c kt thc bi t kha end loop.
te
.4
Begin
L1: loop
L2: loop
exit L2 when (Sec=0);
wait until CLKevent and CLK=1;
Sec:=Sec-1;
198
C_bus (7)
B_bus (7)
A
B_bus (6)
end process;
hoc:
C_bus (6)
.
..
C_bus (0)
om
.v
process ( A, B_bus )
begin
for i in 0 to 7 loop
C_bus (i) <= A and
end loop ;
B_bus (0)
B_bus (i);
end process;
.c
i:=i+1;
end loop ;
B_bus (i);
C_bus (7)
B_bus (7)
A
B_bus (6)
C_bus (6)
..
.
C_bus (0)
B_bus (0)
.4
end process;
and
te
begin
while (i<8) loop
C_bus (i) <= A
ch
process ( A, B_bus )
variable i:integer:=0;
S dng VHDL cho php m t h thng phn cng s theo cc mc tru tng khc
nhau. Hnh v 9-4 m t cc mc m t tru tng gim dn khi s dng VHDL.
+ Mc m t theo m hnh hnh vi (Behavioral): mc m t tru tng cao nht, kiu
m t ny thng dng cho m hnh phn cng v m phng.
+ Mc m t theo m hnh lung d liu RTL (Register Tranfer Level): Kiu m t ny kh
ti u v c cho kh nng tng hp cao, c lp vi cng ngh.
+ Mc m t theo m hnh cu trc logic: Kiu m t ny thng s dng cc cu trc logic
c xy dng sn, hoc chn trong th vin ca nh cung cp ph hp vi loi cng ngh s
dng.
+ Mc m t theo cu trc layout. Mc m t chi tit nht, m t chi tit ti cu trc bn
trong nhng ti nguyn sn c trong cu kin, cch ny ti u cho vic tng hp trn loi cu
kin, cng ngh s dng.
199
Behavioral
RTL
Logic
- M t chi tit hn v
ti u vi cng ngh.
.c
- Nhp thit k v m
phng chm hn
om
.v
AND_OR2
- Nhp thit k v m
phng nhanh hn.
CLB_
R5C5
CLB_
R5C6
ch
Layout
DFF
te
.4
200
+ Khi s dng nh x theo v tr, chng ta a ra danh sch cc tn hiu tun theo ng trt
t m cng c khai bo.
om
.v
.c
- M t triger D nh sau:
ch
entity DFF is
port ( D, Clock : in std_logic ;
Reset : in std_logic ;
Q : out std_logic) ;
end entity DFF ;
Reset
.4
te
201
D_in(2)
D_in(1)
DFF
U2
Q_out(3)
Q_out(2)
DFF
U1
Q_out(1)
DFF
U0
Q_out(0)
Rst
.c
-- nh x theo tn:
U0:DFF port map(Clock =>Clk, D =>D_in(0),
DFF
U3
om
.v
REG_4
entity REG_4 is
port (D_in: in std_logic_vector (3 downto 0);
Clk, Rst: in std_logic;
Q_out: out std_logic_vector (3 downto 0));
end REG_4;
D_in(3)
ch
te
.4
202
Security_1
Keypad
Front_Door
Alarm_Siren
Rear_Door
Window
Clk
Reset
om
.v
entity Security_1 is
port (Clk, Reset : in std_logic ;
Keypad : in std_logic_vector (3 downto 0) ;
Front_Door, Rear_Door, Window: in boolean ;
Alarm_Siren : out boolean ) ;
end Security_1 ;
.4
te
ch
.c
architecture Behavioral of
Security_1 is
constant Delay_Period : time := 20 s;
begin
process (Keypad,Front_Door,Rear_Door,Window)
begin
if (Front_Door or Rear_Door or Window ) then
If (Keypad = 0011) then
Alarm_siren <= false ;
else
Alarm_Siren <= true after Delay_Period ;
end if ;
end if ;
end process ;
end Behavioral;
H thng c biu din theo m hnh RTL bao gm tp cc thanh ghi v cc php ton
c thc hin trn d liu s nh phn c lu trong cc thanh ghi. Lung d liu v vic x l
d liu thc hin trn s liu c cha trong cc thanh ghi c coi nh l hot ng chuyn i
gia cc thanh ghi. V d m hnh RTL ny c s dng biu din cu trc b vi x l. H
thng s c biu din theo m hnh RTL khi chng c xc nh bi 3 thnh phn nh sau:
-
+ Php chuyn i: truyn d liu t thanh ghi ny sang thanh ghi khc.
om
.v
.c
iu khin khi to chui cc php ton bao gm tn hiu nh thi cho php thc hin tun
t cc php ton theo cch c m t trc. C th coi m hnh RTL l m hnh m t hnh
vi theo tng xung clock ca h thng s.
ch
.4
9.3.3.1. M t mch t hp
Combinatorial process
te
Clocked process
Mch logic t hp c th m t bng cc cu trc lnh song,
tuy nhin thng dng cc process t hp. Trong cc process t hp tt c cc tn hiu vo ca
mch t hp phi c a vo danh sch tn hiu kch thch.
begin
-- gn mc nh u ra
D
En
Q <= 0;
if
En = 1 then Q <= D ;
end if ;
end process ;
204
Q <= D ;
En
om
.v
.c
Tin trnh hot ng theo clock c th c m t thnh tin trnh ng b (danh sch tn
hiu kch thch ch c duy nht tn hiu clock, mi bin i ca mch c ng b theo sn
clock) hoc thnh tin trnh khng ng b.
ch
Clk = 1)
then
Clk
.4
te
Reset
end
reset =
elsif
then
end if ;
end if ;
process ;
D
and
Clk = 1) then
then
Q <= D ;
Q <= 0 ;
Clk
Reset
205
om
.v
Tm li biu din h thng s theo m hnh RTL cn s dng cc cu trc thanh ghi
(Registers) v mch t hp (combinational logic), v d t datapath theo m hnh RTL nh hnh
v 9-5 sau:
ch
begin
.c
X1 <= Y0;
X2 <= Y1;
end if;
.4
X3 <= Y2;
te
end process;
begin
Y1 <= F(X1);
Y2 <= G(X2);
end process;
end SPLIT;
206
Registe
rs
process (CLK)
-- Registers
begin
if (CLK'event and CLK = '1') then
Combinational Logic
X2 <= F(X1);
X3 <= G(X2);
X1 <= Y0;
end if;
om
.v
end process;
9.3.4 Phng php m t theo m hnh hnh trng thi (my trng thi State Machine)
.c
STT
- Process t hp
- Xc nh u ra
- Process t hp
- nh gi mi trng thi
- Lnh Case
- nh gi cc iu kin u vo
- Lnh if/else
.4
te
ch
Inputs
Next State
Logic
Current
State
Register
Output
Logic
Outputs
Clock
207
Inputs
Next State
Logic
Output
Logic
Current
State
Register
Outputs
Clock
om
.v
Next State
Logic
Current
State
Reg
te
ch
Clock
Moore
Mealy
Output
Logic
.c
Inputs
.4
. . .
type My_State is ( Init, Load, Fetch, Stor_A, Stor_B) ;
begin
: My_State
: My_State
: My_State
Next_State
begin --architecture
208
:= 111000 ;
:= 101010 ;
:= 000011 ;
: My_State ;
( CLK , RST)
Comb: process
begin
. . .
om
.v
+ Tin trnh kim tra iu kin chuyn i trng thi (tin trnh Comb).
( Curr_State, In1, In2)
.c
te
Outputs: process
begin
. . .
ch
.4
209
UP='0'
S0
RESET
if UP='0' then
Z='1'
else Z='0'
UP='0'
S1
S2
Z='0'
Z='0'
UP='1'
UP='1'
UP='0'
UP='1'
UP='1'
UP='0'
S3
S9
Z='0'
if UP='0' then
Z='0'
else Z='1'
UP='1'
UP='0'
S4
S8
Z='0'
UP='0'
UP='1'
UP='1'
UP='1'
UP='1'
S7
S6
Z='0'
Z='0'
UP='0'
S5
Z='0'
UP='0'
.c
om
.v
Z='0'
UP='0'
UP='1'
UP='0'
USE ieee.std_logic_1164.all;
ENTITY FSM IS
ch
LIBRARY ieee;
te
Z : OUT std_logic);
END;
.4
BEGIN
Sync: PROCESS (CLK)
BEGIN
IF CLK='1' AND CLK'event THEN
210
if RESET='1' then
sreg<= S0;
else
sreg <= next_sreg;
end if;
END IF;
END PROCESS;
Comb: PROCESS (sreg,UP)
BEGIN
WHEN S0 =>
IF ( UP='0' ) THEN
ELSE
WHEN S1 =>
IF ( UP='0' ) THEN
next_sreg<=S0;
next_sreg<=S2;
ch
END IF;
.c
ELSE
IF ( UP='0' ) THEN
ELSE
next_sreg<=S9;
next_sreg<=S1;
END IF;
WHEN S2 =>
om
.v
CASE sreg IS
next_sreg<=S1;
next_sreg<=S3;
te
END IF;
WHEN S3 =>
.4
IF ( UP='0' ) THEN
ELSE
next_sreg<=S2;
next_sreg<=S4;
END IF;
WHEN S4 =>
IF ( UP='0' ) THEN
ELSE
next_sreg<=S3;
next_sreg<=S5;
END IF;
WHEN S5 =>
IF ( UP='0' ) THEN
ELSE
next_sreg<=S4;
next_sreg<=S6;
END IF;
WHEN S6 =>
IF ( UP='0' ) THEN
ELSE
next_sreg<=S5;
next_sreg<=S7;
END IF;
WHEN S7 =>
IF ( UP='0' ) THEN
ELSE
next_sreg<=S6;
next_sreg<=S8;
211
END IF;
WHEN S8 =>
IF ( UP='0' ) THEN
ELSE
next_sreg<=S7;
next_sreg<=S9;
END IF;
WHEN S9 =>
IF ( UP='0' ) THEN
ELSE
next_sreg<=S8;
next_sreg<=S0;
else
Z<= '0';
end if;
ELSE
Z<= '1';
else
Z<= '0';
ch
if sreg=S0 then
END IF;
TM TT
.4
END PROCESS;
te
end if;
END BEHAVIOR;
.c
if sreg=S9 then
om
.v
END CASE;
END IF;
212
CU HI N TP CHNG 8 V CHNG 9
4.
C.
D.
B.
om
.v
B.
C.
Thiu tnh bo mt
D.
.c
A.
A.
CPLD
B.
FPGA
C.
Vi x l
D.
SPLD
ch
te
3.
A.
.4
2.
Mt tch hp cao.
Bo m tnh bo mt ca thit k
B.
1.
D.
C.
5.
6.
A.
B.
Ma trn kt ni
C.
B nh RAM
D.
Triger
B.
B.
C.
D.
Cu trc vo/ra.
B.
C.
D.
om
.v
A.
Nhp thit k, kim tra thit k, tng hp thit k,m phng nh thi, thc hin
thit k, cu hnh.
B.
Nhp thit k, kim tra thit k, thc hin thit k, tng hp thit k, m phng
nh thi, cu hnh.
C.
Nhp thit k, tng hp thit k, kim tra thit k, thc hin thit k, m phng
nh thi, cu hnh.
D.
Nhp thit k, kim tra thit k, tng hp thit k, thc hin thit k, m phng
nh thi, cu hnh.
ch
.c
A.
File m t VHDL
B.
File cu hnh
C.
File netlist
D.
File s mch
10.
Vi x l
te
9.
D.
.4
8.
Ma trn kt ni trung tm
7.
C.
11.
12.
214
A.
File m t VHDL
B.
File cu hnh
C.
File netlist
D.
File s mch
C.
D.
Lp trnh hp ng
B.
Lp trnh bc cao
C.
Lp trnh mng
D.
M t phn cng
om
.v
A.
B.
C.
D.
ch
.c
A.
Lu cc kt qu trung gian
B.
C.
Lu nhng gi tr c nh
D.
Lu cc kt qu trung gian
A.
C.
Lu nhng gi tr c nh
D.
16.
te
15.
B.
.4
14.
13.
A.
17.
A:=1;
B.
A<=1;
C.
A<=1;
D.
A<=true;
215
18.
B.
A:=1;
C.
A<=1;
D.
A:=1;
A.
te
ch
.c
library ieee;
use ieee.std_logic_1164.all;
entity flop is
port(C, D : in std_logic;
Q : out std_logic);
end flop;
architecture archi of flop is
begin
process (C)
begin
if (C'event and C='1') then
Q <= D;
end if;
end process;
end archi;
om
.v
19.
A.
Php gn no ng:
B.
.4
216
C. D
C
D. C
D
20.
CLR
CLR
om
.v
D.
CLR
CLR
.4
te
21.
ch
.c
entity flop is
port(C, D, CLR : in std_logic;
Q
: out std_logic);
end flop;
architecture archi of flop is
begin
process (C, CLR)
begin
if (CLR = '1')then
Q <= '0';
elsif (C'event and C='0')then
Q <= D;
end if;
end process;
end archi;
Q
Q
B. D
C. D
A. D
A.
D
C
B.
D
C
C.
D
C
D.
Q
217
B.
C.
D.
23.
ch
.c
A.
entity flop is
port(C, D, CE : in std_logic;
Q : out std_logic);
end flop;
architecture archi of flop is
begin
process (C)
begin
if (C'event and C='1') then
if (CE='0') then
Q <= D;
end if;
end if;
end process;
end archi;
om
.v
22.
A.
Positive Gate
CLR
Data Output
.4
te
entity latch is
port(G, D, CLR : in std_logic;
Q : out std_logic);
end latch;
architecture archi of latch is
begin
process (CLR, D, G)
begin
if (CLR='1') then
Q <= '1';
elsif (G='1') then
Q <= D;
end if;
end process;
end archi;
218
B.
entity latch is
port(G, D, CLR : in std_logic;
Q : out std_logic);
end latch;
architecture archi of latch is
begin
process (CLR, D, G)
begin
if (CLR='0') then
Q <= '0';
elsif (G='1') then
Q <= D;
end if;
end process;
end archi;
entity latch is
port(G, D, CLR : in std_logic;
Q : out std_logic);
end latch;
architecture archi of latch is
begin
process (CLR, D, G)
begin
if (CLR='1') then
Q <= '0';
elsif (G='1') then
Q <= D;
end if;
end process;
end archi;
entity latch is
port(G, D, CLR : in std_logic;
Q : out std_logic);
end latch;
architecture archi of latch is
begin
process (CLR, D, G)
begin
if (CLR='1') then
Q <= '0';
elsif (G='0') then
Q <= D;
end if;
end process;
end archi;
D.
om
.v
24.
C.
.c
Inverted Gate
ch
PRE
te
.4
entity latch is
port(D : in std_logic_vector(3 downto 0);
G, PRE : in std_logic;
Q : out std_logic_vector(3 downto 0));
end latch;
B.
A.
219
om
.v
D.
ch
.c
25.
C.
te
entity three_st is
port( T, I : in std_logic;
O : out std_logic);
end three_st;
B.
.4
A.
C.
D.
Z;
end archi;
Z;
end archi;
220
26.
B.
downto 0);
begin
process (Clk, CLR)
begin
if (CLR='1') then
tmp <= "0000";
elsif (Clk'event and Clk='1')
then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end archi;
downto 0);
begin
process (Clk)
begin
if (Clk'event and Clk='1')then
om
.v
A.
if (CLR='1') then
tmp <= "0000";
else tmp <= tmp + 1;
ch
.c
end if;
end if;
end process;
Q <= tmp;
end archi;
C.
D.
.4
te
then
Q <= Q + 1;
end if;
end process;
end archi;
downto 0);
begin
process (Clk)
begin
if (Clk'event and Clk='0')then
if (CLR='1') then
tmp <= "0000";
else tmp <= tmp - 1;
end if;
end if;
end process;
Q <= tmp;
end archi;
221
om
.v
entity counter is
port( Clk, S : in std_logic;
Q : out std_logic_vector(3 downto 0));
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (Clk)
begin
if (Clk'event and Clk='1') then
if (S='1') then
tmp <= "1111";
else
tmp <= tmp - 1;
end if;
end if;
end process;
Q <= tmp;
end archi;
27.
ch
.c
.4
te
222
28.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port( Clk, ALOAD : in std_logic; -- Clock v tn hiu np
D : in std_logic_vector(3 downto 0); -- u vo b m
Q : out std_logic_vector(3 downto 0)); -- u ra b m
end counter;
B.
downto 0);
begin
process (Clk,D)
begin
if (ALOAD='1') then
tmp <= D;
elsif (Clk'event and Clk='0')
then tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end archi;
te
ch
downto 0);
.c
begin
process (Clk,ALOAD, D)
begin
if (ALOAD='1') then
tmp <= D;
elsif (Clk'event and Clk='1')
om
.v
A.
C.
D.
architecture archi of counter is
signal tmp: std_logic_vector(3
downto 0);
begin
process (Clk,ALOAD, D)
begin
if (ALOAD='1') then
tmp <= D;
elsif (Clk'event and Clk='0')
downto 0);
begin
process (Clk)
begin
if (ALOAD='1') then
tmp <= D;
elsif (Clk'event and Clk='0')
.4
223
.c
om
.v
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port( Clk, SLOAD : in std_logic;
Q : out std_logic_vector(3 downto 0));
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (Clk)
begin
if (Clk'event and Clk='1') then
if (SLOAD='1') then
tmp <= "1010";
else
tmp <= tmp + 1;
end if;
end if;
end process;
Q <= tmp;
end archi;
29.
te
ch
.4
224
Clock sn dng
PRE
CE
Q[3:0]
u ra d liu 4 bit
D[3:0]
om
.v
30.
.c
library ieee;
use ieee.std_logic_1164.all;
entity flop is
port( C, CE, PRE : in std_logic;
D : in std_logic_vector (3 downto 0);
Q : out std_logic_vector (3 downto 0));
end flop;
B.
ch
A.
C.
D.
.4
te
225
31.
ch
.c
om
.v
entity counter is
port( Clk, SLOAD : in std_logic;
Q : out std_logic_vector(3 downto 0));
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (Clk)
begin
if (Clk'event and Clk='1') then
if (SLOAD='1') then tmp <= "1010";
else
tmp <= tmp + 1;
end if;
end if;
end process;
Q <= tmp;
end archi;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
te
.4
226
32.
B.
om
.v
downto 0);
begin
process (C)
begin
if (CLR='1') then
tmp <= "0000";
elsif (C'event and C='1') then
if (up_down='1') then
tmp <= tmp + 1;
else tmp <= tmp - 1;
end if;
end if;
end process;
Q <= tmp;
end archi;
.4
te
ch
.c
downto 0);
begin
process (C, CLR)
begin
if (CLR='1') then
tmp <= "0000";
elsif (C'event and C='1') then
if (up_down='1') then
tmp <= tmp + 1;
else tmp <= tmp - 1;
end if;
end if;
end process;
Q <= tmp;
end archi;
A.
C.
D.
architecture archi of counter is
signal tmp: std_logic_vector(3
downto 0);
begin
process (C, CLR)
begin
if (CLR='1') then
tmp <= "1111";
elsif (C'event and C='1') then
if (up_down='1') then
tmp <= tmp + 1;
else tmp <= tmp - 1;
end if;
end if;
end process;
Q <= tmp;
end archi;
227
33.
Clk
>
K
C.
entity JKFF is
entity JKFF is
A.
Port(J,K,Clk:in std_logic;
om
.v
Port(J,K,Clk:in std_logic;
Q, notQ:out std_logic);
Q, notQ:out std_logic);
end JKFF;
signal JK:std_logic_vector(0 to
1);
signal JK:std_logic_vector(0 to
1);
.c
end JKFF;
begin
begin
JK<=(J,K);
ch
JK<=(J,K);
process(Clk)
process(Clk)
begin
begin
.4
case JK is
te
case JK is
=>
Null;
when "00"
=>
when "01"
=> Qtemp<='0';
when "01"
=> Qtemp<='0';
when "10"
=> Qtemp<='1';
when "00"
when "10"
=> Qtemp<='1';
when others=>Qtemp<=not
Qtemp;
end case;
end if;
Null;
when others=>Qtemp<=not
Qtemp;
end case;
end if;
end process;
end process;
Q<=Qtemp;
Q<=Qtemp;
notQ<=not Qtemp;
notQ<=not Qtemp;
end Behavioral;
228
end Behavioral;
B.
D.
entity JKFF is
entity JKFF is
Port(J,K,Clk:in std_logic;
Port(J,K,Clk:in std_logic;
Q, notQ:out std_logic);
end JKFF;
begin
begin
process(Clk)
process(Clk)
begin
begin
om
.v
Q<=J; notQ<=K;
end JKFF;
Q<=J; notQ<=K;
end if;
end if;
end process;
end process;
end Behavioral;
end Behavioral;
.c
>
>
>
K1 Q1
K2 Q 2
Clk
K0 Q 0
J2 Q 2
.4
'1'
J1 Q 1
te
J0 Q 0
ch
34.
Q, notQ:out std_logic);
A.
notQ<=not Q;
J(0)<=Q(1) nand Q(2); K(0)<='1';
J(1)<=Q(0);
229
B.
architecture Behavioral of cau33 is
signal Clk: std_logic;
signal J,K,Q,notQ: std_logic_vector(0 to 2);
signal JK0,JK1,JK2: std_logic_vector(0 to 1);
begin
JK0 <=(J(0),K(0));JK1 <=(J(1),K(1));
JK2 <=(J(2),K(2));
J(0)<=Q(1) nand Q(2); K(0)<='1';
K(1)<= notQ(0) nand notQ(2);
C.
architecture Behavioral of cau33 is
begin
.c
process(Clk)
om
.v
J(1)<=Q(0);
begin
ch
when "00"
Null;
=> Q(0)<='0';
te
when "01"
=>
when "10"
=> Q(0)<='1';
.4
end case;
end if;
end process;
end Behavioral;
230
notQ<=not Q;
D.
architecture Behavioral of cau33 is
signal Clk: std_logic;
signal J,K,Q,notQ: std_logic_vector(0 to 2);
signal JK0,JK1,JK2: std_logic_vector(0 to 1);
begin
JK0 <=(J(0),K(0));JK1 <=(J(1),K(1));
JK2 <=(J(2),K(2));
begin
case JK0 is
when "00"
=>
om
.v
process(Clk)
Null;
when "01"
=> Q(0)<='0';
when "10"
=> Q(0)<='1';
=>
Null;
=> Q(1)<='0';
ch
when "01"
.c
end case;
when "10"
=> Q(1)<='1';
te
end case;
case JK2 is
.4
when "00"
=>
Null;
when "01"
=> Q(2)<='0';
when "10"
=> Q(2)<='1';
end case;
end if;
end process;
notQ<=not Q;
J(0)<=Q(1) nand Q(2); K(0)<='1';
J(1)<=Q(0);
231
C.
entity BCDto7seg is
entity BCDto7seg is
Port( BCD:in
Port ( BCD:in
std_logic_vector(3 downto
0);
std_logic_vector(3 downto
0);
Seg : out
Seg : out
std_logic_vector(6 downto
std_logic_vector(6 downto
0));
0));
end BCDto7seg;
end BCDto7seg;
begin
begin
om
.v
--abcdefg"
--abcdefg"
ch
.4
te
w
w
232
x"0",
.c
end Beh;
35.
end Beh;
B.
D.
entity BCDto7seg is
entity BCDto7seg is
Port ( BCD:in
Port ( BCD:in
std_logic_vector(3 downto
0);
std_logic_vector(3 downto
0);
Seg : out
Seg : out
std_logic_vector(6 downto
std_logic_vector(6 downto
0));
end BCDto7seg;
end BCDto7seg;
begin
begin
--abcdefg"
om
.v
0));
--abcdefg"
end Beh;
.4
te
ch
end Beh;
.c
Seg<=
233
36.
C.
entity Mux is
end Mux;
signal I :
std_logic_vector(7 downto
0);
signal I :
signal SEL:
std_logic_vector(8 downto
std_logic_vector(2 downto
0);
0);
signal SEL:
signal Y :std_logic;
0);
om
.v
std_logic_vector(4 downto
begin
signal Y :std_logic;
process
begin
begin
case SEL is
--abcdefg"
I(0) when "0000",
I(1) when "0001",
Y<=I(1);
ch
Y<=I(0);
.c
Y <=
Y<=I(3);
te
Y<=I(2);
.4
end Behavioral;
234
Y<=I(4);
when "101" =>
Y<=I(5);
when "110" =>
Y<=I(6);
when others =>
Y<=I(7);
end case;
end process;
end Behavioral;
B.
D.
entity Mux is
end Mux;
signal I :
std_logic_vector(7 downto
0);
signal I :
signal SEL:
std_logic_vector(7 downto
0);
std_logic_vector(2 downto
0);
signal SEL:
signal Y :
std_logic_vector(2 downto
begin
process(I)
om
.v
signal Y :std_logic;
0);
std_logic;
begin
begin
case SEL is
--abcdefg"
Y <=
Y<=I(0);
te
Y<=I(4);
.4
end Behavioral;
Y<=I(3);
Y<=I(2);
ch
.c
Y<=I(1);
235
p n v hng dn tr li
P N V HNG DN TR LI
CHNG 1
om
.v
1.
2.
3.
4.
5.
6.
CHNG 2
Bi 1.
1. a
2. b
Bi 2.2
.c
1. c
2. b
ch
Bi 2.3
d
te
Bi 2.4
d. Do u bng A+AB
.4
Bi 2.5
Bi 2.6
c
Bi 2.7
c
Bi 2.8
- Nu c khi nim v ti u ho mch in cc h cng
236
p n v hng dn tr li
- Cng c ti u ho
- a ra v d v phn tch hiu qu k thut, kinh t ca vic ti u ho
Bi 2.10
a
Bi 2.11
d
Bi 2.12
om
.v
CHNG 3
1.d
2.a
3.d
4.b
5.c
6.a
8.c
.c
7.b
11.a
w
w
w
10.b
12.d
14.a
1.a
2.d
3.c
4.c
5.c
6.d
7.b
8.c
9.a
10.c
11.a
12.d
13.c
14.a
15.b
16.b
17.a
18.b
19.c
20.d
1.a
2.c
.4
CHNG 4
te
13.d
ch
9.d
CHNG 5
237
4.b
5.d
6.a
7.c
8.d
9.d
10.c
11.a
12.b
13.d
14.c
15.c
16.a
17.d
18.b
19.a
20.a
om
.v
3.c
21.b
22.d
23.b
24.a
25.b
26.c
28.d
.c
27.c
29.c
30.a
te
35.c
32.d
ch
31.b
33.c
34.a
39.b
40.a
.4
CHNG 6
1.c
2.a
3.b
4.d
5.b
6.b
7.c
8.c
9.a
10.d
1.a
2.c
3.c
4.b
5.c
6.a
CHNG 7
238
p n v hng dn tr li
p n v hng dn tr li
7.b
8.a
9.c
10.c
2.D
3.C
4.D
5.C
6.D
7.B
8.D
om
.v
1.C
9.D
10.C
11.B
12.B
15.B
ch
17.C
14.D
18.D
20.D
21.D
22.A
23.C
24.B
te
19.A
.4
w
w
16.A
.c
13.D
CHNG 8 V CHNG 9
25.D
26.A
27.B
28.C
29.C
30.C
31.B
32.A
33.C
34.D
35.A
36.B
239
Mc lc
4. Ton logic v k thut s, Nguyn Nam Qun - Khoa HTC xut bn - 1974
om
.v
8. Digital design principles and practices, John F.Wakerly, Prentice Hall 1990.
.c
10. The Designer's Guide to VHDL by Peter Ashenden, Morgan Kaufmann, 1996.
.4
te
ch
11. Analysis and Design of Digital Systems with VHDL by Dewey A., PWS Publishing,
1993.
240
Mc lc
MC LC
LI GII THIU ................................................................................................................................................. 1
CHNG 1: H M ......................................................................................................................................... 2
GII THIU ...................................................................................................................................................... 2
NI DUNG........................................................................................................................................................ 2
om
.v
.c
ch
te
TM TT........................................................................................................................................................ 26
CU HI N TP.......................................................................................................................................... 26
.4
TM TT........................................................................................................................................................ 43
CU HI N TP.......................................................................................................................................... 43
241
Mc lc
4.8. MCH SO SNH. ................................................................................................................................67
4.9. MCH TO V KIM TRA CHN L. ............................................................................................68
4.10. N V S HC V LOGIC (ALU). ...............................................................................................70
TM TT ........................................................................................................................................................70
CU HI N TP..........................................................................................................................................71
CHNG 5: MCH LOGIC TUN T..........................................................................................................75
GII THIU. ...................................................................................................................................................75
NI DUNG ......................................................................................................................................................75
5.1. KHI NIM CHUNG V M HNH TON HC ............................................................................75
om
.v
.c
ch
TM TT ......................................................................................................................................................116
CU HI N TP CHNG 5...................................................................................................................116
CHNG 6: MCH PHT XUNG V TO DNG XUNG.......................................................................125
te
.4
6.4. IC NH THI....................................................................................................................................134
TM TT ......................................................................................................................................................137
CU HI N TP........................................................................................................................................137
CHNG 7: B NH BN DN...................................................................................................................141
242
Mc lc
NI DUNG.................................................................................................................................................... 156
8.1. GII THIU CHUNG V LOGIC KH TRNH (PLD) ................................................................... 156
8.2 SPLD ................................................................................................................................................... 157
8.3. CPLD (Complex PLD)....................................................................................................................... 157
8.4. FPGA................................................................................................................................................... 159
8.5. SO SNH GIA CPLD V FPGA.................................................................................................... 161
8.6. QUY TRNH THIT K CHO CPLD/FPGA..................................................................................... 161
TM TT...................................................................................................................................................... 168
om
.v
.c
.4
te
ch
MC LC.......................................................................................................................................................... 241
243