EED 206

DIGITAL ELECTRONICS

Spring 2014-15

Lab Test Procedure

1. Each student will individually perform two short tasks one involving the assembly and
demonstration of a circuit using ICs, and the other involving the simulation of a given circuit using
Verilog. Each section will be divided in two rooms for the two types of experiments.
2. The tasks will be based on parts of the experiments done, but will not be exactly the same as those
experiments.
3. The time and marks distribution between the two tasks will be as follows:
(i)

Breadboard duration 100 minutes, 25 marks,

(ii)

Verilog duration 60 minutes, 15 marks.

4. The tasks to be done by a student will be decided by drawing lots. No second option will be given.
5. The individual lab Note-book and all the Experiment write-ups given during the course can be used
by a student during the Lab Test.
6. The marks for the Breadboard task will be based on (i) circuit design (7), (ii) demonstration (10) and
(iii) report giving circuit diagram including pin connections and results (8).
7. The marks for the Verilog task will be based on (i) code written (7) and (ii) demonstration (8).
8. Every student must draw the attention of an instructor as soon as the task is completed, so that the
demonstration can be done well in time. The completion of the report can be done after the
demonstration.