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All Digital Phase Locked Loop Design and

Implementation
Anitha Babu, Bhavya Daya, Banu Nagasundaram, Nivetha Veluchamy
University of Florida, Gainesville, FL, 32608, USA
Abstract An all digital phase locked loop was implemented,
in 0.25 micron CMOS technology, by understanding the analog
phase locked loop concepts and the digital conversion required to
maintain the same functionality. The all digital phase locked loop
achieves locking within about 100 reference clock cycles. The
pure digital phase locked loop is attractive because it is less
sensitive to noise and operating conditions than its analog
counterpart. The implementation and comparison of the digital
and analog phase locked loops are performed in this paper.
Index TermsDigital PLL, DPLL, Phase locked loop, PLL,
Phase frequency detector, DCO

I. INTRODUCTION
Many circuits currently face the problem of clock skew, and
registers and flip-flops are not receiving the clock at the exact
same time. The clocks are generated by oscillators, but the
clocks that reach the registers and flip-flops are distorted and
require a phase locked loop to address this problem. A phase
locked loop ensures that the clock frequencies seen at the
clock inputs of various registers and flip-flops match the
frequency generated by the oscillator.
The phase locked loop (PLL) is a very important and
common part of high performance microprocessors.
Traditionally, a PLL is made to function as an analog building
block, but integrating an analog PLL on a digital chip is
difficult. Analog PLLs are also more susceptible to noise and
process variations. Digital PLLs allow a faster lock time to be
achieved and are attractive for clock generation on high
performance microprocessors.

Figure 1: High Level PLL System Diagram

The all digital phase locked loop was designed such that it is
composed of four main components. The components are

analogous to the analog PLL, but the implementation consists

of digital components. A digitally controlled oscillator (DCO)
was utilized instead of a voltage controlled oscillator. A high
level block diagram of the implementation is shown in Figure
1. 0.25 micron technology was used for the implementation of
this project. The output frequency of the PLL is four times the
input frequency. The supply voltage of the system is 2.5 V.
The Phase Frequency Detector (PFD) detects the phase and
frequency mismatch of the reference clock and divided DCO
clock. The PLL is locked when the PFD detects that the phase
and frequency of the two clock inputs match. The output of the
PFD drives the time to digital (T2D) converter. The PFD
produces up and down enable signals that are interfaced to the
T2D converter. The T2D converter takes these inputs and
increases or decreases the control word which is fed to the
thermometric decoder. This decoder is essential for controlling
the DCO. The DCO clock is divided by a specific
multiplication factor, in our case it is four, and sent back to the
PFD for phase and frequency comparison. The main
components and their implementation will be discussed in the
following sections.
The implementation of the entire PLL doesnt contain any
VHDL based components. All the components were created
schematically and the layout was completed by hand.
II. DESIGN OF PLL SYSTEM COMPONENTS
A. Digital Phase/Frequency Detector
The phase frequency detector is a significant aspect of the
PLL because it determines whether the reference clock and
divided DCO clock are in phase and are running at the same
frequency. The design used is shown in Figure 2.

Figure 2: Phase Frequency Detector Diagram

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A modified D Flip-flop was utilized because the D input
doesnt change and remains high always. The output of the
modified D Flip-flops enters a two input NOR gate that resets
the Flip-flops if both clocks are high. The up and down signals
indicate if the DCO clock needs to be increased (up is true) or
decreased (down is true). The event and direction signal are
necessary to create the up and down enable signals for the
T2D converter. Additional circuitry between the PFD and T2D
is required for the signal conversion to take place.

Figure 3: Output of PFD when Refclk and DCO divided

Clk phase difference varies.
As can be seen in Figure 3, when the phase of the DCO
divided clock varies by a larger margin, the pulse width of the
up signal increases with respect to the phase error. The up
signal contains the phase error because the DCO clock is
falling behind and needs to be increased in frequency to
achieve locking.
The design and understanding of the PFD was important
when continuing with the design and implementation of the
other components of the system.
B. Time to Digital Converter
The time to digital converter consists of a 6 bit down
counter, 6 bit up counter, and 6 bit carry ripple adder. The
phase detector controls the up counter and down counter by up
and down enable signals. The initial state of the up counter is
000000 and the down counter is 111111. The up counter
and down counter values are input into the six bit adder and
the output produces the seven bit control word for the DCO.
Figure 4 shows the connections of the T2D converter. The six
bits from the adder and the carry out bit compose the seven bit
control word. The converter should be active only if there is a
phase and/or frequency mismatch. Clock gating has been
performed to disable the T2D when both the reference clock
and divided DCO clock are locked.
The outputs from the carry ripple adder emerge at different
times. This caused the decoder to interpret its inputs
erroneously. In order to correct this error, a register made of D
flipflops was used to store the outputs from the adder. The
seven bit control word was released from this register based on

the clock given to the counter, delayed by an amount equal to

the propagation delay of the counter and the adder. This
method of synchronizing the adder outputs did not work as
planned and was eliminated from the final PLL system design.
Figure 4: Time to Digital Converter Diagram

C. Thermometric Decoder
The thermometric decoder is a specific decoder that
generates the digital word that controls the DCO. The
thermometric decoder was designed by modifying the general
decoder to obtain the required functionality.
The decoder generates a 128 bit output, of which only 126
bits are used by the DCO. These 126 bits control the DCOs
tristate gates.
D. Digitally Controlled Oscillator
A standard digitally controlled oscillator was implemented,
which consists of a seven stage ring oscillator (in 0.25 micron
technology with an inverter delay close to 20ps and the
frequency of 1.4 GHz) and 21 tristates are parallel to each
inverter. The ring oscillator contains a NAND gate that is used
to control the DCO. This DCO is easy to make using standard
cells, but its power consumption is quite high. In [2], it was
mentioned that fifty percent of the power consumption of a
PLL comes from the DCO.
Figure 5: DCO Consisting of Ring Oscillator and 21
Tristate inverters per inverter.
One of the main design criteria for a DCO is to provide

enough control word resolution and maintain acceptable jitter.

[2] If the resolution is kept small, the jitter of the PLL can be
maintained. Jitter is an important digital PLL performance

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parameter that is simulated for this system.
Our DCO design was tested for all the seven bit input
sequences using a linear feedback shift register. The frequency
corresponding to each control word was noted. The operating
range of the DCO is 180 MHz to 320 MHz. For a control word
of 0000000 the DCO frequency is 48.93 MHz and for
1111111 it is 322.9 MHz. The DCO resolution is close to 1
MHz. Figure 6 displays for each control word the frequency of
the DCO.

lock occurred. The PFD continues to analyze the divided DCO

clock signal with the reference clock signal for any variations.
A frequency or phase variation will cause the PFD to become
activated and the synchronization of two clocks will be
achieved again. Figure 7 shows the schematic of the PLL
system, a better resolution image is attached.
Figure 7: System in Cadence with all Components
IV. RESULTS AND COMPARISONS
The PLL was simulated and found to lock at approximately
1.5 us, when the reference frequency was equal to 70 MHz.
This means the lock occurs in about 105 clock cycles.
When the all digital PLL is compared to an analog PLL
datasheet, from Jameco website, the lock time of an all digital
PLL was found to be much smaller than the 10 us lock time of
an analog PLL. The normalized phase noise for most PLLs
with integrated VCOs was found to be -212 dBc/Hz
(http://www.national.com/cat/index.cgi?i=i//345).
On this website, the maximum supply voltage is shown to be
3.2 V. The cost of the analog PLL is approximately $6.65 each
when thousand ICs are purchased. The output power of an
analog PLL to a 50 ohm load is about 3.5 dBm.

Figure 6: Graph of DCO Analysis

An optimized DCO was developed to be analyzed with
regard to power, but due to time limitations this was not
performed. The optimized DCO should have consumed less
power and resulted in a more energy-efficient PLL.
E. Frequency Divider
The output of the DCO needs to be divided to match the
reference frequency. The implementation contains a divide by
four frequency divider, enabling the PLL to have a
multiplication factor of four. The divider is implemented by
using two series D Flip-flops. The DCO clock is input into
both flip-flops and the non-inverted output of the second flipflop is the DCO clock divided by four.
III. FINAL SYSTEM
The final system is a consolidation of all these components
and extra buffers and circuitry. These main components form
an autonomous system that finds the DCO frequency that is
four times the reference frequency. The final system runs until
the lock is obtained and the T2D is no longer active because

Figure 8: PLL Output and Locking Occurs

The jitter measurement of the PLL is performed by using
Cadence to determine the jitter of the DCO output. The jitter
analysis diagram is shown in Figure 9.

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VI. FUTURE WORK
The VHDL implementation was started in parallel with the
schematic approach. Since the schematic approach of the PLL
required us to perform layout by hand, the VHDL all digital
PLL implementation was left aside. If this was completed, an
analysis could have been performed on the power, area, and
lock time differences of the two implementation approaches.
The thermometric decoder can be made faster; at this point
it is a large and slow decoder that occupies a large part of the
layout. If the decoder can be optimized, the system should be
smaller and more efficient.
The phase maintenance can be used to load the final control
word for the DCO from a register instead of continually
performing phase comparison.
VII. CONCLUSION
The development of an all digital phase locked loop was
interesting and a great learning experience. There are many
improvements and concepts that still need to be learned, but
the basics of an all digital PLL implementation was covered
during this project. A good lock time was achieved of 105
cycles and considerations for power were implemented in this
project.
Figure 9: Jitter Analysis
ACKNOWLEDGMENTS
The area, power and delay of the system, determines the
cost of the phase locked loop. The comparison of the digital
PLL to the analog PLL is shown in Table 1. The area of the
layout is 45666.5 um^2. The power of used by the PLL system
is 3.875 mW, which is equivalent to 5.883 dBm. The number
of transistors in the digital PLL system is 3194.
Table 1: Comparison of Analog and Digital PLL
Digital PLL
Analog PLL
Power
5.883 dBm
3.5 dBm
Lock time
1.5 us
10 us
(100-120 cycles)
Jitter/Phase Noise
0.4 ns
-212 dBc/Hz
The lock time of the digital PLL was observed to be a
great improvement over the analog PLL. The power of the
digital PLL is more than an analog PLL possibly because of
the DCO being used. If a lower power DCO was implemented
into the system, the power could decrease significantly.
V. POWER CONSIDERATIONS
The modified D Flip-flops used for the PFD has lower
power consumption. The clock gating used in the T2D also
saves power.
Other low power implementations can be lowering the
power consumed by the DCO, by using mode selection.
Multiple supply voltages can be used, by having the lower
Vdd supply to the counter, adder, and DCO.

We would like to thank the TA, Tanuj Aggarwal, for his

constant support with debugging simulation errors and logical
errors. Thank you to Professor Bashirullah for making this
learning experience possible.
REFERENCES
[1]

[2]

[3]
[4]
[5]

A Digitally Controlled PLL for SoC Applications Thomas Olsson, and

Peter Nilsson IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.
39, NO. 5, MAY 2004 751
An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable
for High-Performance Microprocessors Jim Dunning,, Gerald Garcia,
Jim Lundberg, and Ed Nuckolls, IEEE JOURNAL OF SOLID-STATE
CIRCUITS, VOL. 30, NO. 4, APRIL 1995
A fully integrated standard-cell digital PLL, T. Olsson and P. Nilsson,
IEEElectron. Lett., vol.37, pp. 211212, Feb. 2001.
J.M. Rabaey, A. Chandrakasan, and B. Nikolic., Digital Integrated
Circuits, 2nd ed.Prentice Hall, 2003, ISBN 0-13-120764-4.
N. Waste and K. Eshraghian, Principles of CMOS VLSI Design,
Addison-Wesley, 1993.