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3 The TTL NAND Gate
3 The TTL NAND Gate
3.1
3.2
Logical Operation
IN1
IN2
T1
T2
T3
T4
OUPUT
LO
LO
ONfor
OFF
OFF
ON
ON
HI
LO
HI
ONfor
OFF
OFF
ON
ON
HI
HI
LO
ONfor
OFF
OFF
ON
ON
HI
HI
HI
ONrev
ON
ON
OFF
OFF
LO
VCC
R3
R1
130
1. 6 k
N5
RB
N3
4k
N1
Input 1
Input 2
T4
N6
N2
T2
T1
N7
N4
Output
(no load)
T3
R2
1k
Fig. 3.2
VCC
I1
IB
I3
R3
130
R1
1.6k
RB
N5
N3
4k
N1
Input 1
Input 2
0.1 V
T4
N6
N2
N7
T1
Output
(no load)
N4
R2
1k
Fig. 3.3
Node N4 :
(v)
VN4 = 0V
The current drawn from the supply can then be obtained as:
IB =
VCC
I1
I3
IB
130
N5
R1
1.6k
RB
N3
4k
N1
Input 1
Input 2
5V
5V
R3
N6
N2
T2
T1
N7
N4
Output
(no load)
T3
R2
1k
Fig. 3.4
Node N2 :
Node N1 :
Node N3 :
Node N5 :
VN5 = VCC = 5V
Node N7 :
The current drawn from the supply this time is given by the sum of IB
and I1 with I3 = 0:
Then:
IB =
and
I1 =
VCC VN3
5 0.9V
=
= 2.56mA
R1
1.6k
PAVE =
POH + POL
5.125 + 16.175
=
= 10.56mW
2
2