This document discusses the architecture and operation of SRAM circuits. It begins by describing the basic 6T SRAM cell architecture and how read and write operations work. It then covers SRAM cell stability theory, defining static noise margin (SNM) and deriving an analytical SNM expression for a 6T cell. Finally, it addresses key SRAM design challenges like variability in the bit-cell and the need for read and write assist circuits.
This document discusses the architecture and operation of SRAM circuits. It begins by describing the basic 6T SRAM cell architecture and how read and write operations work. It then covers SRAM cell stability theory, defining static noise margin (SNM) and deriving an analytical SNM expression for a 6T cell. Finally, it addresses key SRAM design challenges like variability in the bit-cell and the need for read and write assist circuits.
This document discusses the architecture and operation of SRAM circuits. It begins by describing the basic 6T SRAM cell architecture and how read and write operations work. It then covers SRAM cell stability theory, defining static noise margin (SNM) and deriving an analytical SNM expression for a 6T cell. Finally, it addresses key SRAM design challenges like variability in the bit-cell and the need for read and write assist circuits.