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Table of Contents

List of Tables .......................................................................................ix


List of Figures ...................................................................................... x

I.
II.

INTRODUCTION

SRAM CIRCUIT ARCHITECTURE

2.1 SRAM Cell Architecture .....

2.1.1

SRAM ARRAY ARCHITECTURE AND BLOCK STRUCTURE ....... 3

2.1.2

SIX-TRANSISTOR (6T) CMOS SRAM CELL .4

2.2 SRAM Cell Operation . 5

III.

2.2.1

READ OPERATION ...5

2.2.2

WRITE OPERATION 8

SRAM CELL STABILITY THEORY AND DESIGN


CHALLENGES

11

3.1 SRAM Cell Stability Theory .. 11


3.1.1

SNM DEFINITION ... 11

3.1.2

ANALYTICAL SNM EXPRESSION FOR A 6T SRAM CELL 13

3.2 SRAM Design Challenges . 15


3.2.1

VARIABILITY IN THE SRAM BIT-CELL ... 16

3.2.2

READ ASSIST CIRCUITS ... 17

3.2.3

WRITE ASSIST CIRCUITS . 22


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