Points Addressed in this Lecture

General model of finite state machines

FSM design procedure

Lecture 12: Finite State Machines

Professor Peter Cheung
Department of EEE, Imperial College London

E1.2 Digital Electronics I

12.1

Nov 2007

Design of Synchronous Binary Counter

E1.2 Digital Electronics I

synchronous counters use a register to hold the outputs

the inputs of synchronous counters are derived as logical combinations
of outputs
We will now design the counter as a FSM

State Transition Table

Current State
Q2 Q1 Q0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1

Procedure
Step 1: Start with the transition table of the flip-flop to be used

E1.2 Digital Electronics I

Output Transition
Required

Input

0 to 0

0 to 1

1 to 0

1 to 1

12.3

Nov 2007

Step 2: Construct Karnaugh maps for each input from the state
transition table and the flip-flop transition table

From the last lecture we have seen:

E.g. D-type

12.2

Nov 2007

E1.2 Digital Electronics I

Next State
Q2+ Q1+ Q0+
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0

12.4

Nov 2007

 D2
Q2\Q1Q0
0
1

D1

D0

00
0
1

01
0
1

11
1
0

Q2\Q1Q0
0
1

00
0
0

01
1
1

11
0
0

10
1
1

Q2\Q1Q0
0
1

00
1
1

01
0
0

11
0
0

10
1
1

E1.2 Digital Electronics I

Step 3: Extract Boolean expressions from the Karnaugh maps

10
0
1

Q2\Q1Q0
0
1

00
0
1

01
0
1

11
1
0

10
0
1

D2 = Q2. Q1 + Q2. Q1. Q0 + Q2. Q1. Q0

Q2\Q1Q0
0
1

00
0
0

01
1
1

11
0
0

10
1
1

D1 = Q1. Q0 + Q1. Q0 = Q1 Q0

Q2\Q1Q0
0
1

12.5

Nov 2007

00
1
1

E1.2 Digital Electronics I

01
0
0

11
0
0

10
1
1

D0 = Q0
12.6

Nov 2007

Design of Arbitrary Code Counters

Step 4: Implement using combinational logic
Q0
Q1

It may be necessary to design counters which count

sequences other than a binary count
Examples:

1
=1

CLOCK
1
1

E1.2 Digital Electronics I

Q2
Q1
Q2
Q1
Q0
Q2
Q1
Q0

D0
&
&

D1
&

Counters which never reach their maximum value

C1

D2

1D

e.g. a zero-to-nine counter (needs 4 bits)

Q0

Counters which follow a specific code sequence

Q1

e.g. 7 segment display sequence counter

Q2

The design procedure presented for binary counters can

be extended to arbitrary code counters

&

12.7

Nov 2007

E1.2 Digital Electronics I

12.8

Nov 2007

Example
A 3-bit counter to count the decimal sequence
0, 2, 5, 6.
Counting sequence:
Decimal Q2
Q1
0
2
5
6

Current State

State Transition Table

0
0
1
1

0
1
0
1

Q0
0
0
1
0

Next State

Q2

Q1

Q0

Q2+ Q1+ Q0+

Undefined States
In this example, some of the possible 8 states are undefined
What happens if the circuit gets into one of the undefined states?

State Diagram:

e.g. at power-on

We will consider two approaches here:

000

101

010

1.

110

Ignore this possibility

treat the undefined states using "don't care"
Take account of this possibility
map the undefined states explicitly to the "zero" state

2.

In both cases we follow the design procedure already presented

E1.2 Digital Electronics I

12.9

Nov 2007

E1.2 Digital Electronics I

12.10

Nov 2007

Undefined states as "don't care"

Circuit Diagram

D2

CLOCK
Q0
Q1
Q2

D0

D1

C1
1D

Q0

D1

Q1

D2

Q2

D0

C u rre n t S ta te

E1.2 Digital Electronics I

12.11

Nov 2007

N e x t S ta te

Q2\Q1Q0
0
1

00
0
X

01
X
1

11
X
X

Q2\Q1Q0
0
1

00
1
X

01
X
1

11
X
X

10
0
0

Q2\Q1Q0
0
1

00
0
X

01
X
0

11
X
X

10
1
0

Q2

Q1

Q0

Q 2+

Q 1+

Q 0+

D2 = Q0 + Q2. Q1. Q0

D1 = Q1

E1.2 Digital Electronics I

10
1
0

D0 = Q2. Q1
12.12

Nov 2007

Undefined states map to "zero"

Current State
Q2 Q1 Q0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1

Modified State
Transition Table

Modified State
Diagram

111

Q2+
0
0
1
0
0
1
0
0

Next State
Q1+ Q0+
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0

D2

Q2\Q1Q0
0
1

00
0
0

01
0
1

11
0
0

10
1
0

Q2\Q1Q0
0
1

00
1
0

01
0
1

11
0
0

10
0
0

Q2\Q1Q0
0
1

00
0
0

01
0
0

11
0
0

10
1
0

D1

D0

D2 = Q2. Q1. Q0 + Q2. Q1. Q0

D1 = Q2. Q1. Q0 + Q2. Q1. Q0

D0 = Q2. Q1. Q0

100

011

000

001

E1.2 Digital Electronics I

010

101

The term Q 2. Q1. Q 0 can be re-used to simplify the circuitry

This implementation is a bit more complicated but will always work
(unlike the "don't care" implementation)

110

12.13

Nov 2007

E1.2 Digital Electronics I

Implementing FSM with ROM

12.14

Implementing FSM with ROM

Address A2:0

000

101

010

CLOCK
Q0
Q1
Q2

ROM

110

C1
D0
D1
D2

1D

Data D2:0

A2

A1

A0

D2

D1

D0

12.15

All other locations

contain 000

CLOCK

Q0
Q1

Q0

Q2

Q1
Q2

E1.2 Digital Electronics I

Nov 2007

Nov 2007

E1.2 Digital Electronics I

C1
D0

ROM

D1
D2

12.16

1D

Q0
Q1
Q2

Nov 2007