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SN74HC595
SN74HC595
SCLS041G DECEMBER 1982 REVISED FEBRUARY 2004
SN54HC595 . . . J OR W PACKAGE
SN74HC595 . . . D, DB, DW, N, OR NS PACKAGE
(TOP VIEW)
QB
QC
QD
QE
QF
QG
QH
GND
To 15 LSTTL Loads
Low Power Consumption, 80-A Max ICC
Typical tpd = 13 ns
6-mA Output Drive at 5 V
Low Input Current of 1 A Max
Shift Register Has Direct Clear
16
15
14
13
12
11
10
VCC
QA
SER
OE
RCLK
SRCLK
SRCLR
QH
description/ordering information
The HC595 devices contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. The storage register has parallel
3-state outputs. Separate clocks are provided for
both the shift and storage register. The shift
register has a direct overriding clear (SRCLR)
input, serial (SER) input, and serial outputs for
cascading. When the output-enable (OE) input is
high, the outputs are in the high-impedance state.
QC
QB
NC
VCC
QA
SN54HC595 . . . FK PACKAGE
(TOP VIEW)
17
16
15
14
9 10 11 12 13
SER
OE
NC
RCLK
SRCLK
SRCLR
3 2 1 20 19
18
QH
GND
NC
Q H
QD
QE
NC
QF
QG
NC No internal connection
ORDERING INFORMATION
PDIP N
TOP-SIDE
MARKING
Tube of 25
SN74HC595N
Tube of 40
SN74HC595D
Reel of 2500
SN74HC595DR
Reel of 250
SN74HC595DT
Tube of 40
SN74HC595DW
Reel of 2000
SN74HC595DWR
SOP NS
Reel of 2000
SN74HC595NSR
HC595
SSOP DB
Reel of 2000
SN74HC595DBR
HC595
CDIP J
Tube of 25
SNJ54HC595J
SNJ54HC595J
CFP W
Tube of 150
SNJ54HC595W
SNJ54HC595W
LCCC FK
Tube of 55
SNJ54HC595FK
SOIC D
40C to 85C
SOIC DW
55C
55
C to 125
125C
C
ORDERABLE
PART NUMBER
PACKAGE
TA
SN74HC595N
HC595
HC595
SNJ54HC595FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
FUNCTION TABLE
INPUTS
SER
SRCLK
SRCLR
FUNCTION
RCLK
OE
SCLS041G DECEMBER 1982 REVISED FEBRUARY 2004
13
12
10
11
14
1D
C1
R
3R
C3
3S
15
2S
2R
C2
R
3R
C3
3S
2S
2R
C2
R
3R
C3
3S
2S
2R
C2
R
3R
C3
3S
2S
2R
C2
R
3R
C3
3S
2S
2R
C2
R
3R
C3
3S
2S
2R
C2
R
3R
C3
3S
2S
2R
C2
R
3R
C3
3S
QA
QB
QC
QD
QE
QF
QG
QH
QH
Pin numbers shown are for the D, DB, DW, J, N, NS, and W packages.
timing diagram
SRCLK
SER
RCLK
SRCLR
OE
QA
QB
QC
QD
QE
QF
QG
QH
QH
NOTE:
SCLS041G DECEMBER 1982 REVISED FEBRUARY 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA
Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
Supply voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VIL
VI
VO
t/v
NOM
MAX
MIN
NOM
MAX
1.5
1.5
3.15
3.15
4.2
4.2
Output voltage
MIN
VCC = 4.5 V
VCC = 6 V
Input voltage
SN74HC595
0
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
0.5
1.35
1.35
1.8
1.8
0
0
0.5
VCC
VCC
UNIT
VCC
VCC
1000
1000
500
500
400
400
V
V
V
ns
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
VOH
SN74HC595
MIN
2V
1.9
1.998
1.9
1.9
IOH = 20 A
4.5 V
4.4
4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
3.98
4.3
3.7
3.84
3.98
4.3
3.7
3.84
5.48
5.8
5.2
5.34
VI = VIH or VIL
QH, IOH = 4 mA
QH, IOH = 5.2 mA
QAQH, IOH = 7.8 mA
IOL = 20 A
VI = VIH or VIL
QH, IOL = 4 mA
QAQH, IOL = 6 mA
QH, IOL = 5.2 mA
QAQH, IOL = 7.8 mA
4.5 V
6V
5.48
5.8
MIN
MAX
5.2
MIN
MAX
5.34
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
0.17
0.26
0.4
0.33
0.17
0.26
0.4
0.33
0.15
0.26
0.4
0.33
0.15
0.26
0.4
0.33
4.5 V
6V
UNIT
II
IOZ
VI = VCC or 0
VO = VCC or 0,
6V
0.1
100
1000
1000
nA
QAQH
6V
0.01
0.5
10
ICC
VI = VCC or 0,
IO = 0
6V
160
80
10
10
10
pF
Ci
SN54HC595
VCC
QAQH, IOH = 6 mA
VOL
TA = 25C
TYP
MAX
TEST CONDITIONS
2V
to 6 V
SCLS041G DECEMBER 1982 REVISED FEBRUARY 2004
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
fclock
Clock frequency
Pulse duration
SRCLR low
Setup time
SRCLR low before RCLK
th
TA = 25C
MIN
MAX
SN54HC595
MIN
MAX
SN74HC595
MIN
MAX
2V
4.2
4.5 V
31
21
25
6V
36
25
29
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
80
120
100
4.5 V
16
24
20
6V
14
20
17
2V
100
150
125
4.5 V
20
30
25
6V
17
25
21
2V
75
113
94
4.5 V
15
23
19
6V
13
19
16
2V
50
75
65
4.5 V
10
15
13
6V
13
11
2V
50
75
60
4.5 V
10
15
12
6V
13
11
2V
4.5 V
6V
UNIT
MHz
ns
ns
ns
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
FROM
(INPUT)
TO
(OUTPUT)
fmax
SRCLK
QH
H
tpd
RCLK
tPHL
ten
tdis
SRCLR
OE
OE
QAQH
QH
H
QAQH
QAQH
QAQH
tt
QH
H
VCC
MIN
TA = 25C
TYP
MAX
SN54HC595
MIN
MAX
SN74HC595
MIN
2V
26
4.2
4.5 V
31
38
21
25
6V
36
42
25
29
MAX
UNIT
MHz
2V
50
160
240
200
4.5 V
17
32
48
40
6V
14
27
41
34
2V
50
150
225
187
4.5 V
17
30
45
37
6V
14
26
38
32
2V
51
175
261
219
4.5 V
18
35
52
44
6V
15
30
44
37
2V
40
150
225
187
4.5 V
15
30
45
37
6V
13
26
38
32
2V
42
200
300
250
4.5 V
23
40
60
50
6V
20
34
51
43
2V
28
60
90
75
4.5 V
12
18
15
6V
10
15
13
2V
28
75
110
95
4.5 V
15
22
19
6V
13
19
16
ns
ns
ns
ns
ns
tpd
ten
FROM
(INPUT)
RCLK
OE
tt
TO
(OUTPUT)
QAQH
QAQH
QAQH
VCC
MIN
TA = 25C
TYP
MAX
SN54HC595
MIN
MAX
SN74HC595
MIN
MAX
2V
60
200
300
250
4.5 V
22
40
60
50
6V
19
34
51
43
2V
70
200
298
250
4.5 V
23
40
60
50
6V
19
34
51
43
2V
45
210
315
265
4.5 V
17
42
63
53
6V
13
36
53
45
UNIT
ns
ns
ns
TEST CONDITIONS
TYP
UNIT
No load
400
pF
SCLS041G DECEMBER 1982 REVISED FEBRUARY 2004
Test
Point
From Output
Under Test
PARAMETER
RL
CL
(see Note A)
tPZH
ten
1 k
tPZL
tPHZ
tdis
S2
RL
tPLZ
tpd or tt
1 k
Data
Input
VCC
50%
10%
50%
VCC
0V
In-Phase
Output
50%
10%
tPHL
90%
90%
tr
tPHL
Out-ofPhase
Output
90%
tf
Open
Closed
Closed
Open
Open
Open
VCC
th
90%
90%
VCC
50%
10% 0 V
tf
50%
10%
Output
Control
(Low-Level
Enabling)
VCC
50%
50%
0V
tPZL
VOH
50%
10% V
OL
tf
Output
Waveform 1
(See Note B)
tPLZ
90%
VOH
VOL
Output
Waveform 2
(See Note B)
VCC
VCC
50%
10%
tPZH
tPLH
50%
10%
Open
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
50%
tPLH
Closed
tr
VOLTAGE WAVEFORMS
PULSE DURATIONS
50%
Closed
0V
0V
Input
Open
tsu
0V
50%
50 pF
or
150 pF
50%
50%
tw
Low-Level
Pulse
S2
50 pF
or
150 pF
Reference
Input
VCC
50%
S1
50 pF
LOAD CIRCUIT
High-Level
Pulse
CL
VOL
tPHZ
50%
90%
VOH
0 V
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
MECHANICAL DATA
MCFP004A JANUARY 1995 REVISED FEBRUARY 2002
W (R-GDFP-F16)
0.285 (7,24)
0.245 (6,22)
0.045 (1,14)
0.026 (0,66)
0.006 (0,15)
0.080 (2,03)
0.055 (1,40)
0.004 (0,10)
0.019 (0,48)
0.015 (0,38)
16
0.050 (1,27)
0.430 (10,92)
0.370 (9,40)
0.360 (9,14)
0.250 (6,35)
0.360 (9,14)
0.250 (6,35)
4040180-3 / C 02/02
NOTES: A.
B.
C.
D.
E.
MECHANICAL DATA
MLCC006B OCTOBER 1996
FK (S-CQCC-N**)
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
22
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
26
27
28
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
MECHANICAL DATA
MSOI002B JANUARY 1995 REVISED SEPTEMBER 2001
D (R-PDSO-G**)
8 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
0.050 (1,27)
8
0.010 (0,25)
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
0.010 (0,25)
0 8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
0.004 (0,10)
PINS **
0.004 (0,10)
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047/E 09/01
NOTES: A.
B.
C.
D.
MECHANICAL DATA
MSOI003E JANUARY 1995 REVISED SEPTEMBER 2001
DW (R-PDSO-G**)
16 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
9
0.050 (1,27)
16
0.010 (0,25)
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.291 (7,39)
Gage Plane
0.010 (0,25)
1
0 8
0.050 (1,27)
0.016 (0,40)
Seating Plane
0.104 (2,65) MAX
0.012 (0,30)
0.004 (0,10)
PINS **
0.004 (0,10)
16
18
20
24
28
A MAX
0.410
(10,41)
0.462
(11,73)
0.510
(12,95)
0.610
(15,49)
0.710
(18,03)
A MIN
0.400
(10,16)
0.453
(11,51)
0.500
(12,70)
0.600
(15,24)
0.700
(17,78)
DIM
4040000/E 08/01
NOTES: A.
B.
C.
D.
MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
08
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
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