8051 has about 111 instructions.

These can be grouped into the following categories

1. Arithmetic Instructions
2. Logical Instructions
3. Data Transfer instructions
4. Boolean Variable Instructions
5. Program Branching Instructions

The following nomenclatures for register, data, address and variables are used while write instructions.

A: Accumulator
B: "B" register
C: Carry bit
Rn: Register R0 - R7 of the currently selected register bank
Direct: 8-bit internal direct address for data. The data could be in lower 128bytes of RAM (00 - 7FH) or it could be in
the special function register (80 - FFH).
@Ri: 8-bit external or internal RAM address available in register R0 or R1. This is used for indirect addressing mode.
#data8: Immediate 8-bit data available in the instruction.
#data16: Immediate 16-bit data available in the instruction.
Addr11: 11-bit destination address for short absolute jump. Used by instructions AJMP & ACALL. Jump range is 2 kbyte
(one page).
Addr16: 16-bit destination address for long call or long jump.
Rel: 2's complement 8-bit offset (one - byte) used for short jump (SJMP) and all conditional jumps.
bit: Directly addressed bit in internal RAM or SFR
Arithmetic Instructions
Mnemonics

Description

Bytes

Instruction Cycles

ADD A, Rn

A + Rn

ADD A, direct

A + (direct)

ADD A, @Ri

A + @Ri

ADD A, #data

A + data

ADDC A, Rn

A + Rn + C

ADDC A, direct

A + (direct) + C

ADDC A, @Ri

A + @Ri + C

ADDC A, #data

A + data + C

DA A

Decimal adjust accumulator

DIV AB

Divide A by B
A
quotient
B
remainder

DEC A

DEC Rn

Rn

DEC direct

(direct)

DEC @Ri

@Ri

INC A

INC Rn

Rn

INC direct

(direct)

INC @Ri

@Ri

INC DPTR

DPTR

DPTR +1

MUL AB

Multiply A by B
A
low byte (A*B)

A -1

Rn - 1

(direct) - 1

@Ri - 1

A+1

Rn + 1

(direct) + 1

@Ri +1

high byte (A* B)

SUBB A, Rn

A - Rn - C

SUBB A, direct

A - (direct) - C

SUBB A, @Ri

A - @Ri - C

SUBB A, #data

A - data - C

Logical Instructions
Mnemonics

Description

Bytes

Instruction Cycles

ANL A, Rn

A AND Rn

ANL A, direct

A AND (direct)

ANL A, @Ri

A AND @Ri

ANL A, #data

A AND data

ANL direct, A

(direct)

(direct) AND A

ANL direct, #data

(direct)

(direct) AND data

CLR A

00H

CPL A

ORL A, Rn

A OR Rn

ORL A, direct

A OR (direct)

ORL A, @Ri

A OR @Ri

ORL A, #data

A OR data

ORL direct, A

(direct)

(direct) OR A

ORL direct, #data

(direct)

(direct) OR data

RL A

Rotate accumulator left

RLC A

Rotate accumulator left through carry 1

RR A

Rotate accumulator right

RRC A

Rotate accumulator right through carry 1

SWAP A

Swap nibbles within Acumulator

XRL A, Rn

A EXOR Rn

XRL A, direct

A EXOR (direct)

XRL A, @Ri

A EXOR @Ri

XRL A, #data

A EXOR data

XRL direct, A

(direct)

(direct) EXOR A

XRL direct, #data

(direct)

(direct) EXOR data

Data Transfer Instructions

Mnemonics

Description

Bytes

Instruction Cycles

MOV A, Rn

Rn

MOV A, direct

(direct)

MOV A, @Ri

@Ri

MOV A, #data

data

MOV Rn, A

Rn

MOV Rn, direct

Rn

(direct)

MOV Rn, #data

Rn

data

MOV direct, A

(direct)

MOV direct, Rn

(direct)

Rn

MOV direct1, direct2 (direct1)

(direct2)

MOV direct, @Ri

(direct)

@Ri

MOV direct, #data

(direct)

#data

MOV @Ri, A

@Ri

MOV @Ri, direct

@Ri

(direct)

MOV @Ri, #data

@Ri

data

MOV DPTR, #data16 DPTR

data16

MOVC A, @A+DPTR A

Code byte pointed by A + DPTR

MOVC A, @A+PC

Code byte pointed by A + PC

MOVC A, @Ri

Code byte pointed by Ri 8-bit address)

MOVX A, @DPTR

External data pointed by DPTR

MOVX @Ri, A

@Ri

MOVX @DPTR, A

@DPTR

PUSH direct

(SP)

POP direct

(direct)

XCH Rn

A (External data - 8bit address)

(direct)

(SP)

Exchange A with Rn

XCH direct

Exchange A with direct byte

XCH @Ri

Exchange A with indirect RAM

XCHD A, @Ri

Exchange least significant nibble of A with that of 1

indirect RAM

A(External data - 16bit address)

Boolean Variable Instructions

Mnemonics

Description

Bytes

Instruction Cycles

CLR C

C-bit

CLR bit

bit

SET C

SET bit

bit

CPL C

CPL bit

bit

ANL C, /bit

C.

ANL C, bit

C. bit

ORL C, /bit

C+

ORL C, bit

C + bit

MOV C, bit

bit

MOV bit, C

bit

Program Branching Instructions

Mnemonics

Description

Bytes

Instruction Cycles

ACALL addr11

PC + 2

(SP) ; addr 11

AJMP addr11

Addr11

PC

CJNE A, direct, rel

Compare with A, jump (PC + rel) if not equal

CJNE A, #data, rel

Compare with A, jump (PC + rel) if not equal

CJNE Rn, #data, rel

Compare with Rn, jump (PC + rel) if not equal

CJNE @Ri, #data, rel

Compare with @Ri A, jump (PC + rel) if not equal

DJNZ Rn, rel

Decrement Rn, jump if not zero

DJNZ direct, rel

Decrement (direct), jump if not zero

JC rel

Jump (PC + rel) if C bit = 1

JNC rel

Jump (PC + rel) if C bit = 0

JB bit, rel

Jump (PC + rel) if bit = 1

JNB bit, rel

Jump (PC + rel) if bit = 0

PC

JBC bit, rel

Jump (PC + rel) if bit = 1

JMP @A+DPTR

A+DPTR

JZ rel

If A=0, jump to PC + rel

JNZ rel

If A 0 , jump to PC + rel

LCALL addr16

PC + 3

(SP), addr16

LJMP addr 16

Addr16

PC

NOP

No operation

RET

(SP)

PC

RETI

(SP)

PC, Enable Interrupt

SJMP rel

PC + 2 + rel

JMP @A+DPTR
JZ rel
JNZ rel
NOP

A+DPTR
PC
If A = 0. jump PC+ rel
If A 0, jump PC + rel
No operation

1
2
2
1

2
2
2
1

PC

PC

PC