Professional Documents
Culture Documents
SN54/74LS193
PRESETTABLE BCD/DECADE
UP/DOWN COUNTER
PRESETTABLE 4-BIT BINARY
UP/DOWN COUNTER
J SUFFIX
CERAMIC
CASE 620-09
16
1
16
1
P0
15
MR
14
TCD
13
TCU
12
PL
11
P2
10
N SUFFIX
PLASTIC
CASE 648-08
D SUFFIX
SOIC
CASE 751B-03
16
P3
9
ORDERING INFORMATION
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1
P1
2
Q1
3
Q0
4
CPD
5
CPU
6
Q2
7
Q3
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
8
GND
LOGIC SYMBOL
11
PIN NAMES
CPU
CPD
MR
PL
Pn
Qn
TCD
TCU
Ceramic
Plastic
SOIC
15
10
LOADING (Note a)
HIGH
LOW
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
PL
5
CPU
CPD
P0 P1 P2
P3
TCU
12
TCD
13
MR Q0 Q1 Q2 Q3
14
VCC = PIN 16
GND = PIN 8
SN54/74LS192 SN54/74LS193
STATE DIAGRAMS
15
14
TCU = Q0 Q3 CPU
TCD = Q0 Q1 Q2 Q3 CPD
15
14
13
12
11
10
TCU = Q0 Q1 Q2 Q3 CPU
TCD = Q0 Q1 Q2 Q3 CPD
12
11
10
COUNT UP
COUNT DOWN
LS192
LS193
LOGIC DIAGRAMS
P0
PL
(LOAD)
CPU
(UP COUNT)
11
P1
15
P3
9
SD
SD
SD
T
CD Q
CPD
(DOWN
COUNT)
MR
(CLEAR)
P2
10
SD
T
CD Q
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
CD Q
TCD
(BORROW
OUTPUT)
CD Q
Q1
Q2
LS192
13
14
Q0
TCU
(CARRY
OUTPUT)
12
Q3
SN54/74LS192 SN54/74LS193
11
P1
15
P2
P3
10
5
12
SD
SD
SD
T
CD Q
SD
T
CD Q
T
CD Q
CD Q
13
CPD
(DOWN
COUNT)
MR
(CLEAR)
4
14
3
Q0
Q1
Q2
LS193
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
TCU
(CARRY
OUTPUT)
Q3
TCD
(BORROW
OUTPUT)
SN54/74LS192 SN54/74LS193
FUNCTIONAL DESCRIPTION
The LS192 and LS193 are Asynchronously Presettable
Decade and 4-Bit Binary Synchronous UP / DOWN (Reversable) Counters. The operating modes of the LS192 decade
counter and the LS193 binary counter are identical, with the
only difference being the count sequences as noted in the
State Diagrams. Each circuit contains four master/slave
flip-flops, with internal gating and steering logic to provide
master reset, individual preset, count up and count down
operations.
Each flip-flop contains JK feedback from slave to master
such that a LOW-to-HIGH transition on its T input causes the
slave, and thus the Q output to change state. Synchronous
switching, as opposed to ripple counting, is achieved by
driving the steering gates of all stages from a common Count
Up line and a common Count Down line, thereby causing all
state changes to be initiated simultaneously. A LOW-to-HIGH
transition on the Count Up input will advance the count by one;
a similar transition on the Count Down input will decrease the
count by one. While counting with one clock input, the other
should be held HIGH. Otherwise, the circuit will either count by
twos or not at all, depending on the state of the first flip-flop,
which cannot toggle as long as either Clock input is LOW.
PL
CPU
CPD
H
L
L
L
L
X
L
H
H
H
X
X
H
X
X
H
H
MODE
Reset (Asyn.)
Preset (Asyn.)
No Change
Count Up
Count Down
SN54/74LS192 SN54/74LS193
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
TA
54
74
55
0
25
25
125
70
IOH
54, 74
0.4
mA
IOL
54
74
4.0
8.0
mA
Min
P
Parameter
VIH
VIL
VIK
VOH
VOL
IIH
IIL
IOS
ICC
Typ
Max
U i
Unit
2.0
54
0.7
74
0.8
0.65
1.5
T
Test
C
Conditions
di i
Guaranteed Input
p LOW Voltage
g for
All Inputs
54
2.5
3.5
74
2.7
3.5
54, 74
0.25
0.4
IOL = 4.0 mA
74
0.35
0.5
IOL = 8.0 mA
20
0.1
mA
0.4
mA
100
mA
VCC = MAX
34
mA
VCC = MAX
20
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
P
Parameter
Min
Typ
25
32
Max
U i
Unit
fMAX
tPLH
tPHL
CPU Input to
TCU Output
17
18
26
24
ns
tPLH
tPHL
CPD Input to
TCD Output
16
15
24
24
ns
tPLH
tPHL
Clock to Q
27
30
38
47
ns
tPLH
tPHL
PL to Q
24
25
40
40
ns
tPHL
23
35
ns
MHz
T
Test
C
Conditions
di i
50V
VCC = 5.0
CL = 15 pF
SN54/74LS192 SN54/74LS193
AC SETUP REQUIREMENTS (TA = 25C)
Limits
S b l
Symbol
P
Parameter
Min
Typ
Max
U i
Unit
tW
20
ns
ts
20
ns
th
5.0
ns
trec
Recovery Time
40
ns
T
Test
C
Conditions
di i
VCC = 5
5.0
0V
DEFINITIONS OF TERMS
SETUP TIME (ts) is defined as the minimum time required for
the correct logic level to be present at the logic input prior to the
PL transition from LOW-to-HIGH in order to be recognized and
transferred to the outputs.
SN54/74LS192 SN54/74LS193
AC WAVEFORMS
tW
1.3 V
CPU or CPD
tPHL
Q
1.3 V
tPLH
1.3 V
1.3 V
Figure 1
CPU or CPD
Pn
1.3 V
tPHL
tPLH
tPHL
TCU or TCD
1.3 V
Qn
1.3 V
tPLH
1.3 V
NOTE: PL = LOW
Figure 2
Figure 3
1.3 V
Pn
PL
1.3 V
tw
1.3 V
CPU or CPD
tPHL
tPLH
tPHL
1.3 V
Qn
Figure 4
Figure 5
1.3 V
1.3 V
th(H)
ts(H)
ts(L)
th(L)
Q=P
1.3 V
MR
1.3 V
PL
Qn
1.3 V
Pn
trec
tW
PL 1.3 V
tW
trec
1.3 V
CPU or CPD
Q=P
tPHL
Figure 6
1.3 V
Figure 7