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Question Paper Code: W7602

Reg. No. :

M.E. DEGREE EXAMINATION, JANUARY 2010

Applied Electronics

First Semester

AP 9212 ADVANCED DIGITAL SYSTEM DESIGN

(Common to M.E. VLSI Design)
(Regulations 2009)
Time: Three hours

Maximum: 100 Marks

Answer ALL Questions

PART A (10 2 = 20 Marks)

What is the difference between a mealy machine and a Moore machine?

2.

State two reasons why a state table might be incompletely specified.

3.

Define a primitive flow table.

4.

What is the most important consideration in making state assignments for

asynchronous networks?

5.

Define test coverage.

6.

What are propagation D-cuts?

7.

Differentiate the three basic types of PLD.

8.

What are the limitations of PLDs using AND OR structure?

1.

Write down the syntax for declaring a package.

10.

Define test bench.

9.

11.

(a)

Design a sequential circuit to convert BCD to excess 3 codes.

(b)

A Moore sequential network has one input and one output. The output
should be 1 if the total number of 1s received is odd and the total number
of 0s received is an even number greater than 0. Derive the state graph
and table.
(16)

(a)

How can essential hazards be determined and eliminated from a

network?
(16)
Or

(b)

Design a vending machine controller with suitable circuits.

(16)

(a)

Explain the procedure for designing fault-secure PLA with suitable

example.
(16)

13.

12.

(16)

Or

PART B (5 16 = 80 Marks)

Or

Explain how the Boolean difference method is used for test

generation with example.
(8)

(ii)

Explain the logic diagram of built in logic block observer.

14.

(i)

(8)

(a)

Design a 4 bit binary counter using PAL chip.

(b)

(b)

(16)

Explain how FPGA can be programmed to implement a finite state

machine.
(16)

(a)

Using structural modeling write a VHDL for a 4 bit shift register. Also
write a test bench for it.
(16)

Or

15.

Or
Write a VHDL code for the following circuits:

(b)

8 : 1 multiplexer

(ii)

Serial added using finite state machine approach.

(i)

(4)
(12)

W 7602