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  • Memory Organization and Expansion

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    MANIKANDAN
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    This document discusses memory organization and expansion. It describes how address decoding can be achieved using combinational logic, address decoders, or programmable logic devices. It provides two examples of using address decoding to access multiple memory blocks. The first example shows how a 2-4 decoder can be used to decode four 4Kx8 EPROMs from address $0000 to $3FFF. The second example shows how combinational logic and a 2-4 decoder can decode four contiguous 32Kx16 memory blocks starting at address 40000H for an 8086 microprocessor.

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    Memory organization and expansion

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    This document discusses memory organization and expansion. It describes how address decoding can be achieved using combinational logic, address decoders, or programmable logic devices. It provides two examples of using address decoding to access multiple memory blocks. The first example shows how a 2-4 decoder can be used to decode four 4Kx8 EPROMs from address $0000 to $3FFF. The second example shows how combinational logic and a 2-4 decoder can decode four contiguous 32Kx16 memory blocks starting at address 40000H for an 8086 microprocessor.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    14 views4 pages

    Memory Organization and Expansion

    Uploaded by

    MANIKANDAN
    This document discusses memory organization and expansion. It describes how address decoding can be achieved using combinational logic, address decoders, or programmable logic devices. It provides two examples of using address decoding to access multiple memory blocks. The first example shows how a 2-4 decoder can be used to decode four 4Kx8 EPROMs from address $0000 to $3FFF. The second example shows how combinational logic and a 2-4 decoder can decode four contiguous 32Kx16 memory blocks starting at address 40000H for an 8086 microprocessor.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 4

    7/7/2015

    MemoryOrganizationandExpansion

    MemoryOrganizationandExpansion
    Memory can be expanded in both the address and data ranges.

    AddressDecodingcanbeachievedusing:
    1) Combinational Logic, (AND, NAND, OR, NOR and INVERTERS)
    2) Address Decoders (2 to 4, 3 to 8, etc.),
    3) Programmable Logic Device:
    Programmable Logic Array (PLA),
    Programmable Array Logic (PAL),
    Gated Array Logic(GAL).

    EXAMPLE1:
    Show how a single 2line to 4line decoder whose outputs, and a single gate enable input, are
    all active low could be used to fully decode four 4K x 8 EPROMS, having an active low Chip
    Select (/CS) line, from address $0000 to $3FFF. Assume that the system has a 16bit address
    bus and an 8bit data bus.
    First, we will specify all sixteen addresses in binary, showing which address lines will have high
    voltage ("1") and which will have low voltage ("0") for any particular address.

    A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

    $0000 0

    http://www.electronics.dit.ie/staff/tscarff/memory/mem_org_exp.htm

    0 0 0 0 0 0 0 0 0 0
    1/4

    7/7/2015

    BLOCK 0
    BLOCK 1
    BLOCK 2
    BLOCK 3

    MemoryOrganizationandExpansion

    $0FFF 0

    1 1 1 1 1 1 1 1 1 1

    $1000 0

    0 0 0 0 0 0 0 0 0 0

    $1FFF 0

    1 1 1 1 1 1 1 1 1 1

    $2000 0

    0 0 0 0 0 0 0 0 0 0

    $2FFF 0

    1 1 1 1 1 1 1 1 1 1

    $3000 0

    0 0 0 0 0 0 0 0 0 0

    $3FFF 0

    1 1 1 1 1 1 1 1 1 1

    The Truth Table for 2 to 4 Decoder

    http://www.electronics.dit.ie/staff/tscarff/memory/mem_org_exp.htm

    2/4

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    MemoryOrganizationandExpansion

    EXAMPLE2:
    Decoding of the address bus allows the microprocessor to address a single address within a
    block of Memory or Input/Output etc.
    The 8086 microprocessor has a 20bit address bus allowing access to a 1 MByte range.
    Decoding is usually achieved using the unique states of combinational logic, decoders or
    Programmed Logic Arrays. An example of using combinational logic and a 24 decoder is shown
    below:

    http://www.electronics.dit.ie/staff/tscarff/memory/mem_org_exp.htm

    3/4

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    MemoryOrganizationandExpansion

    This is a block diagram showing four contiguous memory blocks of 32k x 16 being decoded to a
    start address of 0100 0000 0000 0000 0000 = 40000H

    http://www.electronics.dit.ie/staff/tscarff/memory/mem_org_exp.htm

    4/4

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