9.7 Let R2 be the resistance seen looking into the collector of Q2 .

Rout = ro1 + (1 + gm1 ro1 ) (r1 k R2 )

Note that this expressoin is maximized as R2 . This gives us
Rout,max = ro1 + (1 + gm1 ro1 ) r1

9.9
1 VA VA VT
(Eq. 9.9)
IC1 VT VA + VT
1 VA
VT
=
IC1 VT
VA
=
IC1

Rout

= ro
This resembles Eq. (9.12) because the assumption that
VA VT
can be equivalently expressed as
VT
VA

IC
IC
ro r
This is the same assumption used in arriving at Eq. (9.12).

9.12
ID = 0.5 mA
Rout = ro1 + (1 + gm1 ro1 ) ro2
!
r
1
1
1
W
=
+ 1 + 2 n Cox ID
ID
L
ID ID
50 k
0.558 V1

9.15 (a)
VD1 = VDD ID RD = 1.3 V > VG1 VT H = Vb1 VT H
Vb1 < 1.7 V
(b)
Vb1 = 1.7 V
VGS1 = Vb1 VX
s
= VT H +

= 0.824 V
VX = 0.876 V

2I

D
n Cox

W
L 1

9.16 (a) Looking down from the source of M1 , we see an equivalent resistance of
Rout = gm1 ro1

1
gm2

k ro2

1
gm2

k ro2 . Thus, we have

(b)
Rout = gm1 ro1 ro2
(c) Putting two transistors in parallel, their transconductances will add and their output resistances
will be in parallel (i.e., we can treat M1 and M3 as a single transistor with gm = gm1 + gm3 and
ro = ro1 k ro3 ). This can be seen from the small-signal model.
Rout = (gm1 + gm3 ) (ro1 k ro3 ) ro2
(d) Lets draw the small-signal model and apply a test source to find Rout .
+

vgs1

gm1 vgs1

ro1

vgs2

gm2 vgs2

+
it

vt

ro2

vgs1
vgs2 + vgs1
= gm1 vgs1 +
ro2
ro1
vgs1 = gm2 ro2 vt it ro2
vt + gm2 ro2 vt it ro2
it = gm1 (gm2 ro2 vt it ro2 ) +
ro1




ro2
1 + gm2 ro2
it 1 + gm1 ro2 +
= vt gm1 gm2 ro2 +
ro1
ro1
it = gm2 vgs2

it (gm1 ro1 ro2 ) = vt (gm1 gm2 ro1 ro2 )

Rout =

1
vt
=
it
gm2

9.17
ID = 0.5 mA
Rout = ro1 + (1 + gm1 ro1 ) ro2
s  
!
W
1
1
1
=
p Cox ID
+ 1+ 2
ID
L 1
ID ID


W
L

= 40 k
 
W
=
= 8
L 2

9.20 (a)
Gm = gm1
Rout =

k ro1

gm2

Av = gm1

1
gm2

k ro1

(b)
Gm = gm2
Rout =

k ro2 k ro1

gm2

Av = gm2

1
gm2

k ro2 k ro1

(c) Lets draw the small-signal model to find Gm .

iout
vin

r1

+
v1

gm1 v1

RE

ro1

vin v1
v1
+
r1
RE
v1 = vin + (iout gm1 v1 ) ro1
v1 (1 + gm1 ro1 ) = vin + iout ro1
vin + iout ro1
v1 =
1 + gm1 ro1
vin + iout ro1
vin
vin + iout ro1

+
iout =
r1 (1 + gm1 ro1 ) RE
RE (1 + gm1 ro1 )




ro1
1
1
ro1
1
iout 1 +
= vin

r1 (1 + gm1 ro1 ) RE (1 + gm1 ro1 )

RE
r1 (1 + gm1 ro1 ) RE (1 + gm1 ro1 )
r1 RE (1 + gm1 ro1 ) + ro1 RE + ro1 r1
r1 (1 + gm1 ro1 ) RE r1
iout
= vin
r1 RE (1 + gm1 ro1 )
r1 RE (1 + gm1 ro1 )
iout [r1 RE (1 + gm1 ro1 ) + ro1 RE + ro1 r1 ] = vin [r1 (1 + gm1 ro1 ) RE r1 ]
iout
Gm =
vin
iout =

r1 (1 + gm1 ro1 ) RE r1
r1 RE (1 + gm1 ro1 ) + ro1 RE + ro1 r1
gm1
(if r1 , ro1 are large)

1 + gm1 RE
= ro2 k [ro1 + (1 + gm1 ro1 ) (r1 k RE )]
=

Rout

Av =

r1 RE (1 + gm1 ro1 ) RE r1
{ro2 k [ro1 + (1 + gm1 ro1 ) (r1 k RE )]}
r1 RE (1 + gm1 ro1 ) + ro1 RE + ro1 r1

(d)
Gm = gm2
Rout = ro2 k [ro1 + (1 + gm1 ro1 ) (r1 k RE )]
Av = gm2 {ro2 k [ro1 + (1 + gm1 ro1 ) (r1 k RE )]}
(e) Lets draw the small-signal model to find Gm .
iout
+
vgs1

gm1 vgs1

RS

vin

ro1

Since the gate and drain are both at AC ground, the dependent current source looks like a resistor
with value 1/gm1 . Thus, we have:
Gm =

1
iout
=
1
vin
k ro1
RS + gm1

RS +

ro1
1+gm1 ro1

1 + gm1 ro1
ro1 + RS + gm1 ro1 RS
gm1

(if ro1 is large)

1 + gm1 RS
= [ro2 + (1 + gm2 ro2 ) RE ] k [ro1 + (1 + gm1 ro1 ) RS ]
=

Rout

Av =

1 + gm1 ro1
{[ro2 + (1 + gm2 ro2 ) RE ] k [ro1 + (1 + gm1 ro1 ) RS ]}
ro1 + RS + gm1 ro1 RS

(f) We can use the result from part (c) to find Gm here. If we simply let r (and obviously we
replace the subscripts as appropriate) in the expression for Gm from part (c), well get the result
we need here.
r2 RE (2 + gm2 ro2 ) RE r2
r2 RE (2 + gm2 ro2 ) + ro2 RE + ro2 r2
gm2 ro2
=
ro2 + RE + gm2 ro2 RE
gm2

(if ro2 is large)

1 + gm2 RE
= [ro2 + (1 + gm2 ro2 ) RE ] k [ro1 + (1 + gm1 ro1 ) RS ]

Gm = lim

r2

Rout

Av =

gm2 ro2
{[ro2 + (1 + gm2 ro2 ) RE ] k [ro1 + (1 + gm1 ro1 ) RS ]}
ro2 + RE + gm2 ro2 RE

(g) Once again, we can use the result from part (c) to find Gm here (replacing subscripts as appropriate).
r2 RE (1 + gm2 ro2 ) RE r2
r2 RE (1 + gm2 ro2 ) + ro2 RE + ro2 r2
gm2

(if r2 , ro2 are large)

1 + gm2 RE
= RC k [ro2 + (1 + gm2 ro2 ) (r2 k RE )]

Gm =

Rout

Av =

r2 RE (1 + gm2 ro2 ) RE r2
{RC k [ro2 + (1 + gm2 ro2 ) (r2 k RE )]}
r2 RE (1 + gm2 ro2 ) + ro2 RE + ro2 r2

9.22
Av = gm1 [ro2 + (1 + gm2 ro2 ) (r2 k ro1 )]
IC1 IC2 = I1

VA1 = VA2 = VA




I1 VA
VA
VT VA
Av
+ 1+
k
VT I1
VT
I1
I1
= 500

VA1 = VA2 = 0.618 V1

9.23 (a) Although the output resistance of this stage is the same as that of a cascode, the transconductance
of this stage is lower than that of a cascode stage. A cascode has Gm = gm , where as this stage
m2
has Gm = 1+ggm2
ro1 .
(b)
Gm =

gm2
1 + gm2 ro1

Rout = ro2 + (1 + gm2 ro2 ) (r2 k ro1 )

Av = Gm Rout
=

gm2
[ro2 + (1 + gm2 ro2 ) (r2 k ro1 )]
1 + gm2 ro1

9.24
Gm = gm1
Rout = ro2 + (1 + gm2 ro2 ) (r2 k ro1 )
Av = gm1 [ro2 + (1 + gm2 ro2 ) (r2 k ro1 )]

9.25 (a)
Gm = gm2

RP k r1
gm1 + RP k r1
1

Rout = ro1 + (1 + gm1 ro1 ) (r1 k ro2 k RP )

Av = gm2

RP k r1
[ro1 + (1 + gm1 ro1 ) (r1 k ro2 k RP )]
gm1 + RP k r1
1

(b)
Gm = gm2
Rout = ro1 k RP + [1 + gm1 (ro1 k RP )] (r1 k ro2 )
Av = gm2 {ro1 k RP + [1 + gm1 (ro1 k RP )] (r1 k ro2 )}
(c)
gm2
1 + gm2 RE
= ro1 + (1 + gm1 ro1 ) [r1 k (ro2 + (1 + gm2 ro2 ) (r2 k RE ))]

Gm =
Rout

Av =

gm2
{ro1 + (1 + gm1 ro1 ) [r1 k (ro2 + (1 + gm2 ro2 ) (r2 k RE ))]}
1 + gm2 RE

(d)
Gm = gm2
Rout = ro1 + (1 + gm1 ro1 ) (r1 k ro2 k ro3 )
Av = gm2 [ro1 + (1 + gm1 ro1 ) (r1 k ro2 k ro3 )]

9.26
Av = gm1 {[ro2 + (1 + gm2 ro2 ) (r2 k ro1 )] k [ro3 + (1 + gm3 ro3 ) (r3 k ro4 )]}


 




IC
VA,N
VA,P
VA,N
N VT VA,N
VA,P
P VT VA,P
=
k
+ 1+
k
+ 1+
k
VT
IC
VT
IC
IC
IC
VT
IC
IC

i h

i
h


VA,P
VA,N
VA,N
VA,P
VA,P
VA,N
N VT
P VT
k IC
k IC
IC + 1 + VT
IC
IC + 1 + VT
IC
IC

i h

i


h
=
V
V
V
VA,P
N VT
P VT
VT VA,N + 1 + VA,N
+ IA,P
k A,N
+ 1 + VA,P
IC
VT
IC
IC
IC k IC
C
T
#"
#
"




N VT VA,N
P VT VA,P
VA,P
VA,N
VA,P
VA,N

V
VA,P
N VT
P VT
IC + 1 + VT
IC + 1 + VT
2
2
IC
IC
+ A,N
IC
IC
IC + IC
IC
# "
#
"
=




VT V

V
V

V
V
V
V
V
N
T
A,N
P
T
A,P
A,P
A,N
A,P
A,N
+

VA,N
VA,P
N VT
P VT
IC + 1 + VT
IC + 1 + VT
2
2
IC

IC

IC

IC

IC

IC

ih


i
V
N VT VA,N
P VT VA,P
VA,P
1
VA,N + 1 + VA,N
V
+
1
+
2
A,P

V
+V
V

V
+V
IC
IC
T
N T
A,N
T
P T
A,P
h


i
h


i
=
VT 1 VA,N + 1 + VA,N N VT VA,N + 1 VA,P + 1 + VA,P P VT VA,P
IC
VT
N VT +VA,N
IC
VT
P VT +VA,P
h


ih


i
VA,N
VA,P
N VT VA,N
P VT VA,P
V
+
1
+
V
+
1
+
A,N
A,P
VT
N VT +VA,N
VT
P VT +VA,P
1
h


i h


i
=
VA,N
VA,P
N VT VA,N
P VT VA,P
VT V
+
1
+
+
V
+
1
+
A,N
A,P
VT
N VT +VA,N
VT
P VT +VA,P

The result does not depend on the bias current.

9.28

|Av |

Av gm1 gm2 ro1 ro2 (Eq. 9.69)

s  
s  

2
W
W
1
= 2
n Cox ID 2
n Cox ID
L 1
L 2
ID
s    
2
W
1
W
= 2n Cox ID
L 1 L 2 ID
s   
1 1
W
W
= 2n Cox
2
ID
L 1 L 2

ID

9.30 From Problem 28, we have

1 1
Av = 2n Cox
ID 2

s

W
L

 
1

W
L

If we increase the transistor widths by a factor of N , we will get a new voltage gain Av :
s
   
W
W
1 1

2
N
Av = 2n Cox
ID 2
L 1 L 2
s   
1 1
W
W
= 2N n Cox
2
ID
L 1 L 2
= N Av
Thus, the gain increases by a factor of N .

9.31 From Problem 28, we have

1 1
Av = 2n Cox
ID 2

s

W
L

 
1

W
L

If we decrease the transistor widths by a factor of N , we will get a new voltage gain Av :
s
   
W
W
1 1
1

Av = 2n Cox
ID 2 N 2 L 1 L 2
s   
1
W
1 1
W
= 2 n Cox
2
N
ID
L 1 L 2
=

1
Av
N

Thus, the gain decreases by a factor of N .

9.32
Gm = gm2
Rout = ro2 k [ro3 + (1 + gm3 ro3 ) ro4 ]
Av = gm2 {ro2 k [ro3 + (1 + gm3 ro3 ) ro4 ]}

9.33
Av = gm1 {[ro2 + (1 + gm2 ro3 ) ro1 ] k [ro3 + (1 + gm3 ro3 ) ro4 ]}
= 500
s  
W
gm1 = gm2 = 2
n Cox ID
L
s  
W
p Cox ID
gm3 = gm4 = 2
L
1
n ID
1
=
p ID

ro1 = ro1 =
ro3 = ro4

ID = 1.15 mA

9.34 (a)
Gm = gm1
Rout = [(ro2 k RP ) + (1 + gm2 (ro2 k RP )) ro1 ] k [ro3 + (1 + gm3 ro3 ) ro4 ]
Av = gm1 {[(ro2 k RP ) + (1 + gm2 (ro2 k RP )) ro1 ] k [ro3 + (1 + gm3 ro3 ) ro4 ]}
(b)
Gm = gm1

ro1 k RP
gm2 + ro1 k RP
1

Rout = [ro2 + (1 + gm2 ro2 ) (ro1 k RP )] k [ro3 + (1 + gm3 ro3 ) ro4 ]

Av = gm1

ro1 k RP
{[ro2 + (1 + gm2 ro2 ) (ro1 k RP )] k [ro3 + (1 + gm3 ro3 ) ro4 ]}
gm2 + ro1 k RP
1

(c)
Gm = gm5
Rout = [ro2 + (1 + gm2 ro2 ) (ro1 k ro5 )] k [ro3 + (1 + gm3 ro3 ) ro4 ]
Av = gm5 {[ro2 + (1 + gm2 ro2 ) (ro1 k ro5 )] k [ro3 + (1 + gm3 ro3 ) ro4 ]}
(d)
Gm = gm5
Rout = [ro2 + (1 + gm2 ro2 ) ro1 ] k [ro3 + (1 + gm3 ro3 ) (ro4 k ro5 )]
Av = gm5 {[ro2 + (1 + gm2 ro2 ) ro1 ] k [ro3 + (1 + gm3 ro3 ) (ro4 k ro5 )]}

9.36
2

1
R2
W
I1 = n Cox
(Eq. 9.85)
VDD VT H
2
L R1 + R2


I1
R2
R2
W
=
VDD VT H
n Cox
VDD
L
R1 + R2
R1 + R2
=

R2
gm
R1 + R2

I1
. Since VGS is
Intuitively, we know that gm is the derivative of I1 with respect to VGS , or gm = V
GS
VGS
is a
linearly dependent on VDD by the relationship established by the voltage divider (meaning V
DD
I1
I1
VGS
I1
VGS
constant), wed expect VDD to also be proportional to gm , since VDD = VDD VGS = VDD gm .

9.37
2
R2
(Eq. 9.85)
VDD VT H
R1 + R2


R2
W
= n Cox
VDD VT H
L R1 + R2

1
W
I1 = n Cox
2
L
I1
VT H

The sensitivity of I1 to VT H becomes a more serious issue at low supply voltages because as VDD
becomes smaller with respect to VT H , VT H has more control over the sensitivity. When VDD is large
enough, it dominates the last term of the expression, reducing the control of VT H over the sensitivity.

9.38 As long as VREF > 0, the circuit operates in negative feedback, so that V+ = V = 0 V.
VREF
IC1 = IS1 eV1 /VT =
R

1
VREF
V1 = VT ln
= VBE2
R1 IS1
If VREF > R1 IS1 , then we have VBE2 < 0, and IX = 0. If VREF < R1 IS1 , then we have:
IX = IS2 e

VT ln

VREF
R1 IS1

/VT

V
ln REF

R1 IS1
= IS2 e
R1 IS1
= IS2
VREF

Thus, if VREF > R1 IS1 (which will typically be true, since IS1 is typically very small), then we get no
output, i.e., IX = 0. When VREF < R1 IS1 , we get an inverse relationship between IX and VREF .

9.39 As long as VREF > 0, the circuit operates in negative feedback, so that V+ = V = 0 V.
VREF
IC1 = IS1 eV1 /VT =
R

1
VREF
V1 = VT ln
= VBE2
R1 IS1
If VREF < R1 IS1 , then we have VBE2 < 0, and IX = 0. If VREF > R1 IS1 , then we have:
V ln

VREF

R1 IS1
IX = IS2 e T
VREF
= IS2
R1 IS1
IS2 VREF
=
IS1 R1
IS2
=
IC1
IS1

/VT

Thus, if VREF < R1 IS1 , then we get no output, i.e., IX = 0. When VREF > R1 IS1 (which will typically
be true, since IS1 is typically very small), we get a current mirror relationship between Q1 and Q2
(ensured by the op-amp).
(with IX copying IC1 ), where the reference current for Q1 is VREF
R1

9.46 (a)
Icopy = 5IC,REF
IREF = IC,REF + IB,REF + IB1
IC,REF
Icopy
= IC,REF +
+

IC,REF
5IC,REF
= IC,REF +
+



5
1
= IC,REF 1 + +



Icopy 6 +
=
5




Icopy =
5IREF
6+

(b)
IC,REF
5
= IC,REF + IB,REF + IB1
IC,REF
Icopy
= IC,REF +
+

IC,REF
IC,REF
+
= IC,REF +

5


1
1
= IC,REF 1 + +

5


6 + 5
= 5Icopy
5


IREF
5
=
6 + 5
5

Icopy =
IREF

Icopy

(c)
3
IC,REF
2
5
I2 = IC,REF
2
IREF = IC,REF + IB,REF + IB1 + IB2
IC,REF
Icopy
I2
= IC,REF +
+
+

3IC,REF
5IC,REF
IC,REF
+
+
= IC,REF +

2
2


3
5
1
+
= IC,REF 1 + +

2
2


2
10 + 2
= Icopy
3
2


3
2
IREF
Icopy =
10 + 2 2
Icopy =

9.49
VGS,REF = VT H +

2IREF
n Cox W
L

VGS1 = VGS,REF I1 RP
s
2IREF
I1 RP
= VT H +
n Cox W
L
s
2IREF
IREF
RP

= VT H +
2
n Cox W
L
!2
s
W
IREF
1
2IREF
RP

I1 = n Cox
2
L
2
n Cox W
L
IREF
s2
IREF
IREF
RP =

2
n Cox W
L
s
s
IREF
2IREF
IREF
RP =

W
2
n Cox W

n Cox L
L
s


IREF
=
21
n Cox W
L

2 21
RP = q
IREF n Cox W
L
=

2IREF
n Cox W
L

Given this choice of RP , I1 does not change if the threshold voltages of the transistors change by the
same amount V . Looking at the expression for I1 in the derivation above, we can see that it has no
dependence on VT H (note that RP does not depend on VT H either).

9.54
IC1 = 1 mA
1 + n
IE1 RE =
IC1 RE = 0.5 V
n
RE == 0.5 V
RE = 495.05
Rout,a = ro1 + (1 + gm1 ro1 ) (r1 k RE )
Rout,b

= 85.49 k
= ro1 + (1 + gm1 ro1 ) (r1 k ro2 )
= 334.53 k

The output impedance of the circuit in Fig. 9.72(b) is significantly larger than the output impedance
of the circuit in Fig. 9.72(a) (by a factor of about 4).

9.56 (a)
Rout = ro1 + (1 + gm1 ro1 ) ro2 = 200 k
1
ro1 = ro2 =
ID
r
W
gm1 = gm2 = 2 n Cox ID
L
 
 
W
W
=
= 1.6
L 1
L 2
(b)
Vb2 = VGS2 = VT H +
= 2.9 V

W
L

2ID
n Cox

9.57 (a) Assume IC1 IC2 , since 1.

Av = gm1 [ro2 + (1 + gm2 ro2 ) (r2 k ro1 )]
I1
gm1 = gm2 =
VT
VA
ro1 = ro2 =
I1
VT
r1 = r2 =
I
" 1 
#

VIT1 VIA1
VA
I1 VA
+ 1+
Av =
VT I1
VT VIT + VIA
1
1




1
VA
VT VA
=
VA + 1 +
VT
VT VT + VA
= 500

VA = 0.618 V
(b)
Vin = VBE1 = VT ln

I1
IS1

= 714 mV
(c)
Vb1 = VBE2 + VCE1
= VBE2 + 500 mV


I1
+ 500 mV
= VT ln
IS2
= 1.214 V

9.58 Assume all of the collector currents are the same, since 1.
P = IC VCC = 2 mW
IC = 0.8 mA
 
IC
Vin = VT ln
= 726 mV
IS

Vb1 = VBE2 + VCE1

 
IC
= VT ln
+ VBE1 VBC1
IS
= 1.252 V
Vb3 = VCC VT ln

IC
IS

= 1.774 V

Vb2 = VCC VEC4 VEB3

= VCC (VEB4 VCB4 ) VT ln

IC
IS

= 1.248 V
Av = gm1 {[ro2 + (1 + gm2 ro2 ) (r2 k ro1 )] k [ro3 + (1 + gm3 ro3 ) (r3 k ro4 )]}
= 4887

9.62
Rout = RC = 500
IC RC
= 20
Av = gm2 RC =
VT
IC = 1.04 mA
P = (IC + IREF ) VCC = 3 mW
IREF = 0.16 mA
AE1
IC =
IREF
AE,REF
AE1
= 6.5

AE,REF

AE,REF = AE
AE1 = 6.5AE

9.63
Icopy = nIC,REF
IREF = IC,REF + IB,REF + IB1
IC,REF
Icopy
= IC,REF +
+

IC,REF
nIC,REF
= IC,REF +
+



n
1
= IC,REF 1 + +



Icopy n + 1 +
=
n




nIREF
Icopy =
n+1+

Since nIREF is the nominal value of Icopy , the error term, n+1+
, must be between 0.99 and 1.01 so
that the actual value of Icopy is within 1 % of the nominal value. Since the upper constraint (that the
error term must be less than 1.01) results in a negative value of n (meaning that we can only get less
than the nominal current if we include the error term), we only care about the lower error bound.

0.99
n+1+
n 0.0101
IREF 50 mA
We can see that in order to decrease the error term, we must use a smaller value for n (in the ideal

). However, the smaller value of

case, we have n approaching zero and the error term approaching 1+
n we use, the larger value we must use for IREF , meaning the more power we must consume. Thus,
we have a direct trade-off between accuracy and power consumption.

9.64
IC,M =

AE,M
IC,REF 1
AE,REF 1

IREF 1 = IC,REF 1 + IB,REF 1 + IB,M

IC,REF 1
IC,M
= IC,REF 1 +
+
n
n
AE,M IC,REF 1
IC,REF 1
+
= IC,REF 1 +
n
AE,REF 1 n


1
AE,M
= IC,REF 1 1 +
+
n
AE,REF 1 n


AE,REF 1
AE,REF 1 n + AE,REF 1 + AE,M
=
IC,M
AE,M
AE,REF 1 n


AE,M
AE,REF 1 n
IREF
IC,M =
AE,REF 1 n + AE,REF 1 + AE,M AE,REF 1
Using a similar derivation to find IC2 , we have:


AE2
AE,REF 2 p
IC,M
IC1 = IC2 =
AE,REF 2 p + AE,REF 2 + AE2 AE,REF 2



AE2
AE,REF 2 p
AE,M
AE,REF 1 p

IREF
=
AE,REF 1 p + AE,REF 1 + AE,M
AE,REF 2 p + AE,REF 2 + AE2 AE,REF 1 AE,REF 2
We want the error term to be between 0.90 and 1.10 so that IC2 is within 10 % of its nominal value.
Since the error term cannot exceed 1 (since we only lose current through the base), we only have to
worry about the lower bound.



AE,REF 1 n
AE,REF 2 p
0.90
AE,REF 1 n + AE,REF 1 + AE,M
AE,REF 2 p + AE,REF 2 + AE2
Lets let the reference transistors QREF 1 and QREF 2 have unit size AE . Then we have:
!
!
n
p
> 0.90
A
p + 1 + AAE2
n + 1 + AE,M
E
E

We can pick any AE,M and AE2 such that this constraint is satisfied. One valid solution is AE,M = AE ,
AE2 = 3.466AE , and IREF = 0.2885 mA. This gives a nominal value for IC2 of 1 mA with an error
of 10 %. This solution is not unique (for example, another solution would be AE,M = AE2 = AE and
IREF = 1 mA, which gives a nominal current of 1 mA and an error of 5.73 %).

9.68
Av = gm1 ro3 = gm1

1
= 20
p ID1

1
k ro2
gm1
ro2
=
1 + gm1 ro2

Rin =

gm1

1
n ID1

1 + gm1 n 1ID1

= 50
= 19.5 mS

ID1 = 4.88 mA
s
 
W
ID1
gm1 = 2n Cox
L 1
 
W
= 390
L 1
We need to size the rest of the transistors to ensure they provide the correct bias current to the amplifier
and to ensure they are all in saturation. VG3 will be important in determining how we should bias
VG5 , since in order for M5 to be in saturation, we require VG3 > VG5 VT Hn , and VG3 is fixed by the
previously calculated value of ID1 .
!
s
2ID1


VG3 = VDD VSG3 = VDD |VT Hp | +
p Cox W
L 3
= 0.363 V

Lets let IREF = ID5 = 1 mA (which ensures we meet our power constraint, since P = (IREF + ID5 + ID1 ) VDD =
12.4 mW) and VGS,REF = VGS5 = 0.5 V (which ensures M5 operates in saturation). Then we have
 
W
1
2
(VGS,REF VT H )
IREF = n Cox
2
L REF
 
 
W
W
360
=
=
L REF
L 5
0.18
(W/L)3
ID3
=
(W/L)4
ID4
 
8.2
W
=
L 4
0.18
(W/L)2
ID2
=
(W/L)REF
IREF
 
W
1756
=
L 2
0.18