module fsm(reset,Pcount,Wtime,empty_flag,full_flag,clk,sens_1,sens_2);

output empty_flag,full_flag;
input clk,sens_1,sens_2,reset;
output Pcount;
output Wtime;
parameter empty=2'b00 , full=2'b11 , between=2'b10 ;
reg [2:0] Pcount ;
reg full_flag,empty_flag;
reg [7:0] Wtime;
wire clk_2;
reg [1:0] state ;
assign clk_2 = sens_1 ^ sens_2;

always @(posedge clk_2)

begin
if(sens_1)
Pcount = Pcount + 1;
else
Pcount = Pcount - 1;
end

always @(posedge clk or posedge reset)

begin
if (reset)
begin
state <= empty ;
empty_flag=0;
full_flag=0;
end
else
case(state)

full:
if (Pcount==6)
state <= between ;
else
begin
empty_flag =0;
full_flag =1;
end

empty: if (Pcount ==1) state <= between;

else
begin
empty_flag = 1;
full_flag =0;
end
between: if (Pcount==0)
state <= empty ;
else if (Pcount==7)
state <= full ;
else
begin
state <= between;
//assign Wtime = rom [Pcount];

empty_flag=0;
full_flag=0;
end
endcase

end
endmodule