Digital Design

Lab
2010
Experiment #5
Adders And Subtractors 2

By:
www.hms-ppu.com www.hms-ppu.com
www.hms-ppu.com www.hms-ppu.com

To:
Eng.Alaa Al
0

.Exp#4
Adders and Subtractors 2

Tamimi

28-10-2010
Experiment Title:

Adders and Subtractor 2

Objectives:

- To be familiar with the construction of the magnitude comparator

and decimal adder using adder-subtractor
- Building these circuits using Circuit Maker 2000 SW & describing it
using Verilogger pro.
- To be familiar with the educational kit and Quartus SW to download
the HDL code to the kit.

.Exp#4
Adders and Subtractors 2

Decimal Adder:
A4

5V
0V

A3
A2
A1
B4
B3

A4
A3
A2
A1
B4
B3
B2
B1

5V
0V
0V
0V

B2

U3
74LS83

s4
s3
s2
s1

A4
A3
A2
A1
B4
B3
B2
B1

Cin Cout

0V

B1
Cin

U1
74LS83

0V

S4 S3 S2 S1

s4
s3
s2
s1

Cin Cout

0V

OPcarry

DISP1
L1
KPD1

4321

3
4321

U1
74LS83

A4
A3
A2
A1
B4
B3
B2
B1

KPD2
1
4321

U3
74LS83

s4
s3
s2
s1

A4
A3
A2
A1
B4
B3
B2
B1

Cin Cout

s4
s3
s2
s1

Cin Cout

Cin

0V

OPcarry

BCD Adder

.Exp#4
Adders and Subtractors 2

Magnitude Comparator:
V1
5V
V2
5V

Data
Input

V3
0V

U3B

U1
74LS83

V4
5V
V6
5V

U2A

Data
Input

V5
5V

U2B

V7
5V

U2C

V9
5V

A4
A3
A2
A1
B4
B3
B2
B1

U3C
s4
s3
s2
s1

U3D

Cin Cout

U3E

L1

A=b

U4A

U3F

L3

A>B

U5A

U2D

L2
V8
5V

U3A

A<B

A
KPD1
9
4321

B
KPD2
8
4321

74LS83

A4
A3
A2
A1
B4
B3
B2
B1

L1

A=B

U4A
s4
s3
s2
s1

U3F

Cin Cout

L3

A>B
L2
U3A

V1
5V
+V

.Exp#4
Adders and Subtractors 2

A<B

The End

.Exp#4
Adders and Subtractors 2