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FULL ADDER Using Gates

Micro Project Report

Title: FULL ADDER Using Gates

1.0 Introduction:
In the realm of digital electronics, arithmetic operations form the backbone of
computational tasks, ranging from simple calculations to complex algorithms. One
fundamental building block in this domain is the Full Adder, a crucial component used
for binary addition. A Full Adder is an essential piece of the puzzle when it comes to
designing circuits that perform arithmetic operations on binary numbers.
We will embark on a journey to understand the fundamental concept of a Full Adder,
explore its basic building blocks, delve into its truth table, and discuss its
implementation using basic logic gates. This report aims to equip the reader with a
thorough understanding of Full Adders and their role in digital computation, enabling
them to appreciate the elegance of digital circuit design and its practical significance in
today's technology-driven world

2.0 Aim of Project:


The project aims to enhance understanding of digital logic design, reinforce the
principles of binary addition, and provide valuable insights into the operation and
optimization of Full Adder circuits using basic logic gates.

3.0 Course Outcomes:

CO1: Designing Digital Circuits.

CO2: Digital System Testing and Verification.

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SHARAD INSTITUTE OF TECHNOLOGY, POLYTECHNIC YADRAV
FULL ADDER Using Gates

CO3: Problem Solving.

CO4: Teamwork and Project Work.

4.0 Literature Review:


The full adder is a fundamental building block in digital electronics and plays a crucial
role in arithmetic and logic operations. It is a combinational circuit that adds three
binary digits: two inputs (A and B) and a carry input (Cin) to produce two outputs (Sum
and Cout). The full adder can be implemented using a variety of methods, with the use
of basic logic gates being one of the most traditional and versatile approaches.

5.0 Actual Methodology Followed:


1. Formation of groups.
2. Selected topic for project.
3. Prepared proposal.
4. Collection of information.
5. Started Queries

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SHARAD INSTITUTE OF TECHNOLOGY, POLYTECHNIC YADRAV
FULL ADDER Using Gates

6.0 Actual Resources Used:

SR.NO Name of Specifications Quantity Remarks


Resources

1. Breadboard 5.5cm X 17cm 1 Yes

2. Power Supply 5+ V 1 Yes

3. IC 7486 1 Yes

4. IC 7408 1 Yes

5. IC 7432 1 Yes

6. LED RED 5mm 2 Yes

7. Resistors 320 Ω, 0.25 W 2 Yes

8. Connecting Teflon coated AS Yes


Wires Required

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SHARAD INSTITUTE OF TECHNOLOGY, POLYTECHNIC YADRAV
FULL ADDER Using Gates

7.0 Theoretical Background

7.1 Working

Full Adder is the adder that adds three inputs and produces two outputs. The first two inputs are
A and B and the third input is an input carry as C-IN. The output carry is designated as C-OUT
and the normal output is designated as S which is SUM. The C-OUT is also known as the
majority 1’s detector, whose output goes high when more than one input is high.

A full adder logic is designed in such a manner that can take eight inputs together to create a
byte-wide adder and cascade the carry bit from one adder to another. we use a full adder
because when a carry-in bit is available, another 1-bit adder must be used since a 1-bit half-
adder does not take a carry-in bit. A 1-bit full adder adds three operands and generates 2-bit
results.

Fig 1. Block Diagram

7.2 Truth Table

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FULL ADDER Using Gates

7.3 K-map

SUM = A XOR B XOR C

CARRY = (A B) + (B C) + (A C)

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SHARAD INSTITUTE OF TECHNOLOGY, POLYTECHNIC YADRAV
FULL ADDER Using Gates

8.0 Circuit Diagram: -

Fig 2. Circuit Diagram

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SHARAD INSTITUTE OF TECHNOLOGY, POLYTECHNIC YADRAV
FULL ADDER Using Gates

9.0 Step-by-Step Procedure:

1. Place the Logic Gates:

Position the XOR gates, AND gates, and OR gate on the breadboard. Ensure they are
securely connected to the power supply (VCC) and ground (GND) pins.

2. Connect the Power Supply:

Connect the VCC pin of the ICs to the positive rail of the breadboard and the GND pin to
the ground rail. Ensure proper power connections.

3. Connect Input Switches:

Connect the three input switches (for A, B, Cin) to the breadboard. Connect one terminal of
each switch to the power rail (VCC) and the other terminal to the input pins of the XOR
and AND gates.

4. Connect Output LEDs:

Place the LED indicators for Sum and Cout on the breadboard. Connect one leg of each
LED to the output of the XOR and OR gates. Connect a current-limiting resistor in series
with the LEDs and then connect the other leg of the LEDs to the ground rail.

5. Connect Logic Gates:

Connect the inputs and outputs of the XOR gates, AND gates, and OR gate according to the

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SHARAD INSTITUTE OF TECHNOLOGY, POLYTECHNIC YADRAV
FULL ADDER Using Gates
logic diagram of a full adder. Connect the output of the XOR gates to the Sum LED and the
output of the OR gate to the Cout LED.

6. Set Inputs and Observe Outputs:

Set the input switches to different combinations of 0 and 1 (for A, B, and Cin) and observe
the Sum and Cout LEDs. Verify that they respond correctly according to the full adder truth
table.

7. Test with Arithmetic Operations:

You can also test the full adder's functionality by connecting two full adders to perform
binary addition. This involves cascading the Cout of the first full adder to the Cin of the
second one.

8. Secure and Organize:

Ensure all connections are secure, and wires are organized to minimize interference and
confusion.

By following these steps, we have implemented a FULL ADDER circuit on a breadboard.


Always be cautious with power connections and ensure the correct wiring of gates and
components to achieve the desired functionality.

10.0 Precautions Followed:

Do not switch ON the power supply unless you have checked the circuit
connections as per the circuit diagram.

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SHARAD INSTITUTE OF TECHNOLOGY, POLYTECHNIC YADRAV
FULL ADDER Using Gates

11.0 Conclusion: -
The " FULL ADDER Using Gates " project successfully designed and implemented. The
implementation of a Full Adder using basic logic gates is an essential learning experience for
anyone interested in digital electronics. It exemplifies the beauty of digital logic, where
complex operations can be broken down into a sequence of simpler steps, and it showcases the
power of logic gates in creating functional and scalable digital systems.

12.0 Reference: -
1. https://chat.openai.com/
2. https://bard.google.com/?utm_source=sem&utm_medium=paid-
media&utm_campaign=q3enIN_sem6
3. Guided by Ms. S. S. Malame

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SHARAD INSTITUTE OF TECHNOLOGY, POLYTECHNIC YADRAV
FULL ADDER Using Gates

Project Diary

BY

Ms. Tasmiya Firoj Nadaf 25034


Ms. Vedika Mahesh Nagarkar 25035
Ms. Varsha Sanjay Nimbalkar 25036
Ms. Samedha Adinath Patil 25037

Students
Sr.no Date Work done Hours Guide sign
sign
1. 10-7-23 At first, we made the 15 min
group of 5 members.

2. 20-7-23 Searched Project 1 hour


Subject.

3. 28-7-23 We took suggestions 15 min


from our guide for
selecting our project

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SHARAD INSTITUTE OF TECHNOLOGY, POLYTECHNIC YADRAV
FULL ADDER Using Gates
4. 15-8-23 After selection of 1 hour
project topic wise
searched the basic
information related to it

5. 30-8-23 Then the collection of 1 hour


information was done. 30 min

6. 5-9-23 Later we visited to our 30 min


guide for suggesting us
some more
information on topic
and some corrections
in collected
information.
7. 10-9-23 If there were some 1 hour
corrections then it was
corrected.

8. 15-9-23 After correcting it, we 30 min


again visited our guide
to show the corrections.

9. 20-9-23 Then we started 1 hour


searching some more
information on the
topic (for gaining some
more knowledge).

10. 25-9-23 We had a visit to our 30 min


guide after searching
some information.

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SHARAD INSTITUTE OF TECHNOLOGY, POLYTECHNIC YADRAV
FULL ADDER Using Gates
11. 5-10-23 Some suggestions were 30 min
guided and we tried to
make it correct as per
the guide's requirement.

12. 12-10-23 After making some 20 min


changes we again had a
visit to our guide.

13. 15-10-23 Then we started 1 hour


implementing it on the 30 min
required Software

14. 18-10-23 Then by that time, we 40 min


made the project report.

15. 20-10-23 We had visited to our 1 hour


guide to present our
project.

16. 23-10-23 Then we finally 1 hour


submitted our project
and project report till
this date.

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SHARAD INSTITUTE OF TECHNOLOGY, POLYTECHNIC YADRAV

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