Scribd Logo
Upload

Welcome to Scribd!

  • Pflop: Dge-Triggered Er-Slave Conce R. The S of The Clock

    Uploaded by

    Harshal Ambatkar
    11 views2 pages
    The document describes a D-flipflop circuit based on a master-slave concept that is insensitive to clock overlap. It uses a Clocked CMOS (C2MOS) latch design where clock overlaps activate either the pull-up or pull-down networks but not both simultaneously. For slow clocks, there is a timing slot where both NMOS and PMOS transistors conduct, creating a path between input and output that can destroy the state. Simulations show the circuit operates correctly if the clock rise/fall time is less than 5 times the propagation delay to avoid a race condition.

    Original Description:

    dsvlsi 3.3

    Original Title

    Experiment No. 3.3

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    The document describes a D-flipflop circuit based on a master-slave concept that is insensitive to clock overlap. It uses a Clocked CMOS (C2MOS) latch design where clock overlaps activate either the pull-up or pull-down networks but not both simultaneously. For slow clocks, there is a timing slot where both NMOS and PMOS transistors conduct, creating a path between input and output that can destroy the state. Simulations show the circuit operates correctly if the clock rise/fall time is less than 5 times the propagation delay to avoid a race condition.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    11 views2 pages

    Pflop: Dge-Triggered Er-Slave Conce R. The S of The Clock

    Uploaded by

    Harshal Ambatkar
    The document describes a D-flipflop circuit based on a master-slave concept that is insensitive to clock overlap. It uses a Clocked CMOS (C2MOS) latch design where clock overlaps activate either the pull-up or pull-down networks but not both simultaneously. For slow clocks, there is a timing slot where both NMOS and PMOS transistors conduct, creating a path between input and output that can destroy the state. Simulations show the circuit operates correctly if the clock rise/fall time is less than 5 times the propagation delay to avoid a race condition.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 2

    3.

    D-Flipflop

    Above figure show


    ws an ingeniou
    us positive ed
    dge-triggered register, baseed on a masteer-slave conceept
    insensitive to clock oveerlap. This cirrcuit is called
    d the ( Clocked CM
    MOS) registerr. The

    latch is in
    nsensitive to clock
    c
    overlapss because thosse overlaps acctivate either the pull-up oor the pull-dow
    wn
    networks of the latchess, but never both of them simultaneouslly. If the rise aand fall timess of the clock are
    sufficientlly slow, howeever, there ex
    xists a time slo
    ot where bothh the NMOS aand PMOS traansistors are
    conductin
    ng. This createes a path betw
    ween input an
    nd output that can destroy tthe state of thhe circuit.
    Simulations haave shown thaat the circuit operates
    o
    correectly as long as the clock rrise time (or ffall
    time) is sm
    maller than ap
    pproximately five times the propagationn delay of thee register. Thiis criterion is not
    too stringent, and is easily met in prractical design
    ns. For slow cclocks, the pootential for a rrace conditionn
    exists.
    VDD

    Schematiic Diagram:
    M5

    M7

    CLK
    VDD

    M4
    CLK

    Data

    val0=1.8
    val1=0.0

    M6
    CLKBAR

    Data

    Data

    CLK

    VDD

    val0=1.8
    val1=0

    gnd

    VDD

    M9
    M1
    CLKBAR

    M3
    CLK
    CLK

    CLKBAR
    M8

    M0

    M2

    gnd

    gnd

    Date/Time Run: 4/9/2016 4:57:45 PM


    1.8
    1.6
    1.4
    1.2
    V

    1
    0.8
    0.6
    0.4
    SEL>>
    -0.1

    CLK
    1.8
    1.6
    1.4
    1.2
    V

    1
    0.8
    0.6
    0.4
    0.2
    0

    Data
    2.229
    2
    1.6

    1.2
    0.8
    0.4
    0
    -0.238
    0

    4n

    8n

    12n

    16n

    20n

    Q
    time, s
    SymSpice

    24n

    28n

    32n

    36n

    40n

    You might also like