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Timing Analysis for Engineers

This document discusses system level timing analysis for a circuit. It analyzes the setup and hold times for FF2 to ensure it meets timing under worst-case conditions. It assumes propagation delays for each path and component. It calculates setup time as the clock period minus the slowest data path plus the fastest clock. It calculates hold time as the fastest data path minus the slowest clock. Minimum delays are questionable and should be assumed 0 ns unless guaranteed. Skew effects need more examination as parts get faster.

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Mahesh
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140 views9 pages

Timing Analysis for Engineers

This document discusses system level timing analysis for a circuit. It analyzes the setup and hold times for FF2 to ensure it meets timing under worst-case conditions. It assumes propagation delays for each path and component. It calculates setup time as the clock period minus the slowest data path plus the fastest clock. It calculates hold time as the fastest data path minus the slowest clock. Minimum delays are questionable and should be assumed 0 ns unless guaranteed. Skew effects need more examination as parts get faster.

Uploaded by

Mahesh
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

System Level Timing Analysis

System Level Timing Analysis 1


Required Timing Analyses

B
D Q D Q

FF1 FF2
G1 G2
A C

CLK
TCLK=CLK Period

The circuit must be analyzed to show that the set-up (tSU) and
hold (tH) times of FF2 are met under worst-case conditions.

System Level Timing Analysis 2


Analysis Assumptions
• The propagation delay of G1, tPDG1, includes all the
delays from CLK to the clock input of FF1:
tPDG1 = The connection delay from CLK to G1 input
+ delay of G1 itself
+ connection delay from G1 output to FF1
clock input
• Similarly for G2
• Similarly, tPDFF1 includes the connection delay from
the FF1 output to FF2 input

System Level Timing Analysis 3


Set-up Time Analysis

tSU@FF2 = TCLK - Slowest Data + Fastest CLK


= TCLK - (tPDG1Max + tPDFF1Max) + tPDG2Min

tPDDataMax
tPDG2Min
CLK
B
C
tSU

System Level Timing Analysis 4


Hold Time Analysis
tH@FF2 = Fastest Data - Slowest CLK
= tPDG1Min + tPDFF1Min - tPDG2Max

tPDDataMin

CLK

C
tH
tPDG2Max

System Level Timing Analysis 5


Hold Time Support

Optional delay is matched


to the clock distribution
delay to make tH = 0 ns.
System Level Timing Analysis 6
Clock Skew
• If the clock is slower than the data, then the wrong value will
be transferred from FF1 to FF2

• tH@FF2 = tPDG1Min + tPDFF1Min - tPDG2Max < 0


If tPDG2Max > tPDG1Min + tPDFF1Min

Should latch this Latches this instead

CLK
tPDDATA
B
C tPDCLK
tH < 0

System Level Timing Analysis 7


Using Minimum Delays
• In the tSU and tH equations, the minimum
delays are questionable
– Minimum delays are supplied by some vendors
but not all.
• If no guaranteed minimum delay value
exists, then the correct value to use is 0 ns.

System Level Timing Analysis 8


Minimum Delays and Skew

• Given that tPDMin=0 should be assumed


unless guaranteed otherwise, we have
tH@FF2 = tPDG1Min + tPDFF1Min - tPDG2Max < 0
= 0 + 0 – tPDG2Max < 0
which is true for any tPDG2Max > 0.
⇒ Circuits should be more carefully examined for
skew effects now that parts are getting faster.

System Level Timing Analysis 9

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