STA Fundamentals

Agenda

▪ Timing Paths
▪ Setup/Hold check
▪ Required Arrival Time, Actual Arrival Time and Slack
▪ I/O Timing Analysis
Timing Paths

What is timing point ?

▪Node at which timing data is present
What is a Timing path?
▪A timing path is a point-to-point path in a design which can propagate data from from
one flip-flop to another
▪Each path has a startpoint and an endpoint
▪Startpoints (Input ports, Clock pins of flip-flops)
▪Endpoints ( Output ports Data input pins of flip-flops)

Timing Point

INPUT
OUTPUT
D Q D Q
FF1 FF2

CLOCK
Setup & Hold Times

CLK
DATA PRE
D Q Tsu Th

CLK CLR DATA Valid

Setup Time: the amount of time the synchronous input (D) must be stable
before the active edge of clock

Hold Time: the amount of time the synchronous input (D) must be stable
after the active edge of clock.

Together, the setup time and hold time form a Data Required Window, the
time around a clock edge in which data must be stable.

[Source : Altera’s Timing Analysis Introduction presentation]

Setup Time

▪ Setup Margin
▪ The data valid time available after meeting the setup requirement
Hold Time

▪ Hold Margin
▪ The data valid time available after meeting the hold requirement
Arrival Time, Required Time & Slack

Arrival time:
• Time elapsed for a signal to arrive at a certain point.
• To calculate the arrival time, delay calculation of all the component of the
path will be required.

Required time:
• Latest time at which a signal can arrive without making the clock cycle
longer than desired.

Slack:
• It is the difference between the required time and the arrival time.
• This is the amount of time by which a violation is avoided
• E.g.: for a setup constraint, if a signal must reach a cell input at no later
than 8 ns and is determined to arrive at 5 ns, the slack is 3 ns.
• A slack of 0 means that the constraint is just barely satisfied.
• A negative slack indicates a timing violation.
Setup & Hold Violations
▪ Two types of violation :
▪ Hold violation
▪ Setup Violation

Hold violation is caused when the clock travels slower than the path from
one register to another – allowing data to penetrate two registers in the
same clock tick, or might destroy the integrity of the latched data.

Setup Violation is caused if the data signal gets delayed from the source
flip-flop, so that the data signal has that much less time to reach the
destination flip-flop before the next clock tick.

Which is more dangerous – setup violation or hold violation?

Data Arrival Time

▪ The time for data to arrive at destination register’s D input

▪ Data Arrival Time = launch edge + Tclk1 + Tco +Tdata
REG1 Tdata REG2
PRE Comb. PRE
D Q Logic D Q
Tclk1
CLR CLR

TCO
Launch
Edge

Tclk1
REG1.CLK Tco
REG1.Q Data Valid
Tdata
REG2.D Data Valid

[Source : Altera’s Timing Analysis Introduction presentation]

Clock Arrival Time

▪ The time for clock to arrive at destination register’s clock input

▪ Clock Arrival Time = latch edge + Tclk2

REG1 REG2
PRE Comb. PRE
D Q Logic D Q

CLR CLR

Tclk2

Latch
Edge
CLK Tclk2

REG2.CLK

[Source : Altera’s Timing Analysis Introduction presentation]

Data Required Time - Setup

▪ The minimum time required for the data to get latched into the destination
register
▪ Data Required Time = Clock Arrival Time – Tsu
REG1 REG2
PRE Comb. PRE
D Q Logic D Q

CLR CLR

Tclk2

Latch
Edge
CLK Tclk2
Data must be
valid here Tsu
REG2.CLK

[Source : Altera’s Timing Analysis Introduction presentation]

REG2.D Data Valid
Data Required Time - Hold

▪ The minimum time required for the data to get latched into the destination
register
▪ Data Required Time = Clock Arrival Time + Th
REG1 REG2
PRE Comb. PRE
D Q Logic D Q

CLR CLR

Tclk2 Th
Latch
Edge
CLK Tclk2
Data must
remain valid Th
to here
REG2.CLK

REG2.D Data Valid

[Source : Altera’s Timing Analysis Introduction presentation]

Setup Slack

▪ The margin by which the setup timing requirement is met. It ensures

launched data arrives in time to meet the latching requirement.
REG1 Tdata REG2
PRE Comb. PRE
D Q Logic D Q
Tclk1
CLR CLR

Launch TCO Tclk2 Tsu

Edge Latch
Edge
CLK Tclk1
REG1.CLK Tco
REG1.Q Data Valid
Tdata
REG2.D Data Valid
Tclk2
Tsu
REG2.CLK
Setup
Slack

[Source : Altera’s Timing Analysis Introduction presentation]

Setup Slack (cont’d)
▪ Setup Slack = Data Required Time – Data Arrival Time

Positive slack
▪ Timing requirement met

Negative slack
▪ Timing requirement not met

CALCULATION:
Arrival time (max) = clock delay FF1 (max) +clock-to-Q delay FF1 (max) + comb. Delay( max)
Required time = clock adjust + clock delay FF2 (min) - set up time FF2
Slack = Required time - Arrival time (since we want data to arrive before it is required)
clock adjust = clock period (since setup is analyzed at next edge)
Hold Slack

▪ The margin by which the hold timing requirement is met. It ensures latch
data is not corrupted by data from another launch edge. It also prevents
“double-clocking”.
REG1 Tdata REG2
PRE Comb. PRE
D Q D Q
Logic
Tclk1
CLR CLR

TCO Tclk2 Th

Next Launch Latch

Edge Edge
CLK Tclk1
REG1.CLK Tco
REG1.Q Data Valid
Tdata
REG2.D Data Valid
Th Hold
Tclk2 Slack
REG2.CLK

[Source : Altera’s Timing Analysis Introduction presentation]

 Hold Slack (Cont’d)
▪ Hold Slack = Data Arrival Time – Data Required Time

Positive slack
▪ Timing requirement met

Negative slack
▪ Timing requirement not met

CALCULATION:
Arrival time = clock delay FF1 (min) +clock-to-Q delay FF1 (min) + comb. Delay( min)
Required time = clock adjust + clock delay FF2 (max) + hold time FF2
Slack = Arrival time - Required time (since we want data to arrive after it is required)
clock adjust = 0 (since hold is analyzed at same edge)
Hold Checks and Setup Check Cycles

▪ A hold timing check ensures that:

▪ Data from the subsequent launch edge must not be captured by the setup
receiving edge
▪ Data from the setup launch edge must not be captured by the preceding
receiving edge

Launch edge 1 Launch edge 2

Launch flip-flop clock

Setup check 1 Hold check 1

Hold 0
Capture flip-flop clock

Capture edge 0 Capture edge 1

Recovery & Removal

▪ Recovery time is the minimum time that an asynchronous control must be

stable before the clock active-edge transition, when async signal is
deasserted.

▪ Removal time is the minimum length of time that an asynchronous control

must be stable after the clock active-edge transition, when async signal is
deasserted.
SET
D Q

CLK CLR

ASYNC

clock

recovery time removal time

async_in
Asynchronous Reset/Set signal
▪ The critical asynchronous signal in any design is the Reset.
▪ Meeting reset recovery and removal time is mandatory, much like the
setup/hold time of D input with respect to the trigger edge of clock.
▪ For an asynchronous active low reset/set pin of a Flip-Flop:
▪ Recovery Time (much like setup time) is the minimum time that the asynchronous
reset must remain deasserted (high) BEFORE the active edge of the clock for the
proper functioning of the flip-flop. The cell is considered functional as long as the
delay for the output reaching its expected value does not exceed the reference delay
(measured with a large recovery time) by more than 10%.
▪ Removal Time (much like hold time) is the minimum time that the asynchronous
reset must remain asserted (low) AFTER the active edge of the clock for proper
functioning of the flip-flop. The cell is considered functional as long as the active
clock edge does not latch in the new data value from that programmed by the
asynchronous set or reset signal.
I/O Analysis

▪ Analyzing I/O performance in a synchronous design uses the same slack

equations
▪ Must include external device & PCB timing parameters

Data Arrival
Path

ASSP or FPGA/CPLD FPGA/CPLD or ASSP

reg1 reg2
PRE Tdata PRE
D Q D Q
CL*
CLR CLR

TCO Tsu/Th

Tclk2 Data
Data Arrival Required
Path Path
OSC

[Source : Altera’s Timing Analysis Introduction presentation]

How many timing paths?

Path 1 Path 2 Path 3

Path 4
▪ Path 1 starts at an input port and ends at the data input of a sequential
element.
▪ Path 2 starts at the clock pin of a sequential element and ends at the data
input of a sequential element.
▪ Path 3 starts at the clock pin of a sequential element and ends at an
output port.
▪ Path 4 starts at an input port and ends at an output port.
How many timing paths? (Cont’d)

▪ Register to Register
▪ Input port to Register
▪ Set the data arrival time at the port
▪ Register to Output port
▪ Set the port external delay
▪ Input port to Output port

Input to Reg Reg to Reg

IN_1 OUT_1
FF1
IdlClk

Reg to Output
FF2

Input to Output
[Source : Timing
IN_2Analysis Basics presentation from Cadence] OUT_2
Understanding Timing Paths: Reg to Reg

Gate + Wire delay

D Q D Q

Clock to Q _ Setup _
C Q Time C Q

Clock Period

[Source : Timing Analysis Basics presentation from Cadence]

Understanding Timing Paths: Input to Reg

▪ Input Delay = clk --> q t comb1

Outside World Block Being Constrained
Input Delay Gate + Wire delay

Clock to Q
D Q Comb1 Comb2 D Q

_ Setup
_
C Q Gate + Time C Q
Wire delay

0 Clock
Root
Clock Period

[Source : Timing Analysis Basics presentation from Cadence]

Understanding Timing Paths: Reg to Output

▪ External_delay = comb delay + setup

▪ External_delay = comb delay - hold time

Block Being Constrained Outside World

External Delay
Clock to Q
D Q D Q
Comb1

_ _
Setup
C Q Gate + Gate + Time
C Q
Wire delay Wire delay

0 Clock
Root Clock Period

[Source : Timing Analysis Basics presentation from Cadence]

Understanding Timing Paths: Input Port to Output
Port

▪ Input delay and output delay are set with respect to a clock
▪ Default single-cycle
▪ Setup requirement:
▪Comb delay < clock period - input delay - external delay
▪ Hold requirement:
▪Comb delay > clock period - input delay - external delay
▪ Combinational paths have no clocks defined for the module
▪ Setup requirement:
▪Comb delay =< (delay set with set_path_delay_constraint -late) - input_delay -
external_delay
▪ Hold requirement:
▪Comb delay >= (the delay set with set_path_delay_constraint -early) - input_delay -
external_delay

[Source : Timing Analysis Basics presentation from Cadence]

STA in RTL to GDSII flow
Thank You!!