数字集成电路原理

Timing Issues

刘佳欣
liujiaxin@uestc.edu.cn
Outline
pTiming Basics
pTiming Constraints: Max and Min Delays
pTiming Borrow
pClock Non-idealities

2
Synchronous Timing

C L K

I n C o m b
R1 R2
Ci n
L o go
C u Ot u t i

3
Asynchronous Timing

4
Synchronous Timing Methods

pRegister-
based

p2-Phase
Latch-based

5
Synchronous Timing Methods

pRegister-
based

p2-Phase
Latch-based

6
Timing Parameters - Latch

D Q

Clk

T
Clk PWm
tsetup
D thold

tpcq tpdq
Q

Delays can be different for rising and falling data transitions

7
Timing Parameters - Register

D Q

Clk

Tc
Clk

thold
D
tsetup
tpcq
Q

Delays can be different for rising and falling data transitions

8
Timing Parameters

9
Outline
pTiming Basics
pTiming Constraints: Max and Min Delays
pTiming Borrow
pClock Non-idealities

10
Max Delay: Registers-Based
p Max delay needs to satisfy the clock frequency requirement

tpcq + tpd + tsetup <= Tc

11
Min Delay: Registers-Based
p Min delay needs to satisfy the hold time requirement

12
Max Delay: 2-Phase Latches-Based

tpdq1 + tpd1 + tpdq2 + tpd2 <= Tc

13
Min Delay: 2-Phase Latches-Based

14
Outline
pTiming Basics
pTiming Constraints: Max and Min Delays
pTiming Borrow
pClock Non-idealities

15
Time Borrowing Concept
pIn a register-based system
• Data launches on one clock rising/falling edge
• Data must be setup before next rising/falling edge
• If it arrives late, system fails
• If it arrives early, time is wasted
• Robust and reliable, easy to use, supported by all tools

16
Time Borrowing Concept
pIn a latch-based system
• Data can pass through latch while transparent
• Latch is a ‘soft’ barrier
• One stage can pass slack or borrow time from other stages
• Significant performance advantages

17
Latch-Based Design

18
Slack-Borrowing

19
Time-Borrowing Example
p Assume register/latch delay << combinatorial logic delay

Register-based Ts,min = 125ns

design

CLK

20
Time-Borrowing Example

Latch-based Ts,min = ?
design

Ts = 83.3ns

CLK

21
Time-Borrowing Example

22
Outline
pTiming Basics
pTiming Constraints: Max and Min Delays
pTiming Borrow
pClock Non-idealities

23
Clock Skew & Clock Jitter

p Clock skew
Ø Spatial variation in arrival time of a clock transition at
different points
Ø Static variation

p Clock jitter
Ø Temporal variations of the clock period at a given point
Ø Dynamic random variation

24
Soueces of Skew and Jitter

① Clock generation: noise in VCO

② Process variation
③ Interconnect variation
④ Power supply noise
⑤ Temperature variation
⑥ Capacitive load
⑦ Coupling to adjacent lines
25
Soueces of Skew and Jitter

26
Clock Skew
p Positive and negative clock skew

27
Time Constraints Due to Clock Skew

Max: tpcq + tpd + tsetup <= Tc + δ Min: tccq + tcd > thold + δ

Negative skew avoids system failures but hampers the circuit performance!
28
Datapath Structure with Feedback
pRouting the clock so that only negative skew occurs is
not feasible
pDesign of a low-skew clock network is essential

29
Clock Jitter
pJitter is time-varing
pJitter is a zero-mean random variable

pAbsolute jitter：tjitter
pCycle-to-cycle jitter
Ø Worst cycle-to-cycle is 2 times of absolute jitter tjitter
30
Time Constraints due to Clock Jitter

Max: tpcq + tpd + tsetup <= Tc - 2tjitter

Min: tccq + tcd > thold + 2tjitter

31
Impact of Skew + Jitter

Max: tpcq + tpd + tsetup <= Tc + δ - 2tjitter

Min: tccq + tcd > thold + δ + 2tjitter

32
Thank you!