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Input D Q Combo D Q
ck Launch Flop ck Capture Flop Out
clock
Setup Time – It is the minimum time required for the input data that must be stable before the
Setup time
Required Time – It is the Time required for the input data must be available before the setup
Time.
clk
clk
clk
T(C2Q+combo)
clk
Setup time
clk
T(C2Q+combo)
clk
Setup time
Required Time
Setup slack
Launch flop :- It is the flop flip at which the input data will be launched with respect to
launch edge of clock.
Capture flop :- It is the flop flip at which the input data will be catured with respect to
capture edge of clock.
Single cycle path :- The path at which data arrives one T(time period) time after the launch
edge
positive Launch edge
clock
clock
In Multi cycle path required time = Capture clock delay +2T - setuptime
Half cycle path :- The path at which data arrives T/2(time period) time after the launch edge
positive Launch edge
clock
In to R
IN1 R to R path
D Q
R to Out path
r1
A1 Y out1
Ck D Q
clk1 A2 U2 ck r3
AAAAA
in to R path
In2
D Q A Y
clk2 R to R Path
Ck r2 U1
clk3
In3 A Y out2
U3 In to out path
As we can see the various timing path in the (Design A) Named as,
clk1
clk1
Required Time
Time period(clk1)
CLK1
CLK3
Required Time
Time period(clk3)
Arrival Time = (clk1 to CLK)delay + (Clk to Q)delay + Combinational delay
Clk3
Clk3
Clk3 to CLK
CLK
CLK
CLK to out2