INTRODUCTION TO SEQUENTIAL LOGIC

 The present state and the external circuit determine the

output and the next state of sequential circuits.

 Thus in sequential circuits, the output variables depend

not only on the present input variables but also on the
past history of input variables.

Sequential Circuit- Block Diagram

 INTRODUCTION TO SEQUENTIAL LOGIC
Combinational vs Sequential Circuit

S.No Combinational logic Sequential logic

The output variable, at all times The output variable depends not only
1 depends on the combination of on the present input but also depend
input variables. upon the past history of inputs.

Memory unit is required to store the

2 Memory unit is not required
past history of input variables.

3 Faster in speed Slower than combinational circuits.

4 Easy to design Comparatively difficult to design.

Eg. MUX, Decoder, Parallel Eg. Counter, Shift Register, Serial

5
adder adder
 FLIP-FLOPS
Triggering of Flip flops
 There are two types of level triggered latches:
 (i). Positive level triggered: The output of the latch responds to
the input changes only when the enable input is 1(HIGH).

 (ii). Negative level triggered: The output of the latch responds to

the input changes only when the enable input is 0 (LOW).
 FLIP-FLOPS
Triggering of Flip flops
 Edge Triggering: In the edge triggering the output responds to the
changes in the input only at the positive or negative edges of the clock
pulse at the clock input.

 (i). Positive edge triggering: Here the output responds to the

changes in the input only at the positive edge of the clock pulse at the
clock input.

 (ii). Negative edge triggering: Here the output responds to the

changes in the input only at the negative edge of the clock pulse at
the clock input.
 FLIP-FLOPS
Flip flops
 The basic 1-bit digital memory circuit is known as a flip-
flop. Flip-Flops are synchronous bistable devices (has two
outputs Q and Q’).

 In this case, the term synchronous means that the output

changes state only at a specified point on the triggering
input called the clock (CLK), i.e., changes in the output
occur in synchronization with the clock. It can have only
two states, either the 1 state or the 0 state.
 FLIP-FLOPS
Flip flops

 Flip-flops can be obtained by using NAND or NOR gates.

 If Q is 1 i.e., Set, then Q' is 0; if Q is 0 i.e., Reset, then Q' is 1. That

means Q and Q' cannot be at the same state simultaneously.

 There are different types of flip-flops depending on how their inputs

and clock pulses cause transition between two states.

 We will discuss four different types of flip-flops SR, D, JK, and T.

 Basically D, J-K, and T are three different modifications of the S-R flip-
flop.
 S-R FLIP-FLOP
 When S is HIGH and R is LOW, the Q output goes HIGH on the
triggering edge of the clock pulse, and the Flip-Flop is SET.

 When S is LOW and R is HIGH, the Q output goes LOW on the

triggering edge of the clock pulse, and the Flip-Flop is RESET.

 When both S and R are LOW, the output does not change from its prior
state.

 An invalid condition exists when both S and R are HIGH.

S-R FLIP-FLOP
FLIP-FLOPS
SR Flip flops
 FLIP-FLOPS
SR Flip flops
module SR_FF(Q,QB,S,R,CLK);
input S,R,CLK;
output Q,QB;
reg Q,QB;
always @(posedge CLK)
begin
case({S,R})
2'b00:Q=Q;
2'b01:Q=0;
2'b10:Q=1;
2'b11:Q=1'bx;
endcase
QB=~Q;
end
endmodule
 FLIP-FLOPS
TEST BENCH
module
module SR_FF_TB;
reg S,R,CLK;
wire Q,QB;
SR_FF uut (.Q(Q), .QB(QB), .S(S), .R(R), .CLK(CLK) );
always #100 CLK=~CLK;
initial begin
CLK=1;
#200 S=1; R=0;
#200 S=0; R=0;
#200 S=0; R=1;
#200 S=1; R=1;
end
endmodule
 D FLIP-FLOP
 In D Flip-Flop, the basic SR Flip-Flop is used with
complemented inputs.
 To eliminate the undesirable condition of the indeterminate
state in the RS Flip-Flop is to ensure that inputs S and R
are never equal to 1 at the same time. This is done by D
Flip-Flop.
 The D (delay or data) Flip-Flop has one input called delay
input and clock pulse input.
D FLIP-FLOP
D FLIP-FLOP
 D FLIP-FLOP

module D_FF(Q,QB,D,CLK); module D_FF_TB;

input D,CLK; reg D;
output Q,QB; reg CLK;
reg Q,QB; wire Q;
always @(posedge CLK) wire QB;
begin D_FF uut (.Q(Q), .QB(QB), .D(D), .CLK(CLK));
Q=D; always #100 CLK=~CLK;
QB=~Q; initial begin
end CLK=1;
endmodule #200 D=1;
#200 D=0;
end
endmodule
 J-K FLIP-FLOP
 JK means Jack Kilby, Texas Instrument (TI) Engineer, who
invented IC in 1958.
 JK flip-flop is built using only NAND gates.
 JK Flip-Flop has two inputs J(set) and K(reset).
J-K FLIP-FLOP
J-K FLIP-FLOP
J-K FLIP-FLOP
 J-K FLIP-FLOP
module JK_FF(Q,QB,J,K,CLK); module JK_FF_TB;
input J,K,CLK; reg J;
output Q,QB; reg K;
reg Q,QB; reg CLK;
always @(posedge CLK) wire Q;
begin wire QB;
case({J,K}) JK_FF uut (.Q(Q), .QB(QB), .J(J), .K(K),
2'b00:Q=Q; .CLK(CLK));
2'b01:Q=0; always #100 CLK=~CLK;
2'b10:Q=1; initial begin
2'b11:Q=~Q; CLK=1;
endcase #200 J=1;K=0;
QB=~Q; #200 J=0; K=0;
end #200 J=0; K=1;
endmodule #200 J=1; K=1;
end
endmodule
 T FLIP-FLOP

 The T (Toggle) Flip-Flop is a modification of the JK Flip-

Flop. It is obtained from JK Flip-Flop by connecting both
inputs J and K together, i.e., single input.

 Regardless of the present state, the Flip-Flop

complements its output when the clock pulse occurs while
input T= 1.
T FLIP-FLOP
T FLIP-FLOP
 T FLIP-FLOP
module T_FF(Q,QB,T,CLK); module T_FF_TB;
input T,CLK; reg T;
output Q,QB; reg CLK;
reg Q=0,QB; wire Q;
always @(posedge CLK) wire QB;
begin T_FF uut (.Q(Q), .QB(QB),
case(T) .T(T),.CLK(CLK));
1'b0:Q=Q; always #100 CLK=~CLK;
1'b1:Q=~Q; initial begin
endcase CLK=1;
QB=~Q; #200 T=0;
end #200 T=1;
endmodule #200 T=0;
#200 T=1;
end
endmodule
Summary of FLIP-FLOPS
 COUNTERS
TYPES OF COUNTER
 Flip-Flops can be connected together to perform
counting operations. Such a group of Flip- Flops is a
counter.

 The number of Flip-Flops used and the way in which

they are connected determine the number of states
(called the modulus)
 Counters are classified into two broad categories
according to the way they are clocked:
Asynchronous counters
Synchronous counters.
 COUNTERS
TYPES OF COUNTER

 In asynchronous (ripple) counters, the first Flip-Flop is

clocked by the external clock pulse and then each
successive Flip-Flop is clocked by the output of the
preceding Flip-Flop.

 In synchronous counters, the clock input is connected to

all of the Flip-Flops so that they are clocked
simultaneously.

 Within each of these two categories, counters are

classified primarily by the type of sequence, the number of
states, or the number of Flip-Flops in the counter.
 COUNTERS
SYNC. Vs ASYNC. COUNTER
S.No Asynchronous (ripple) counter
1 All the Flip-Flops are not clocked
simultaneously.
2 The delay times of all Flip-Flops
are added. Therefore there is
considerable propagation delay.
3 Speed of operation is low
4 Logic circuit is very simple even
for more number of states.
5 Minimum numbers of logic
devices are needed.
6 Cheaper than synchronous
counters.
Synchronous counter
All the Flip-Flops are clocked
simultaneously.
There is minimum propagation delay.
Speed of operation is high.
Design involves complex logic circuit as
number of state increases.
The number of logic devices is more than
ripple counters.
Costlier than ripple counters.
 COUNTERS
2-BIT SYNC. UP COUNTER
 COUNTERS
2-BIT SYNC. UP COUNTER
 COUNTERS
Design steps of synchronous counter

• Find the number of flip flops using 2n ≥ N,

where N is the number of states and n is the
number of flip flops
• Choose the type of flip flop
• Draw the state diagram of the counter
• Draw the excitation table of the selected flip
flop and determine the excitation table for the
counter
• Use K-map to derive the flip flop input
functions
 COUNTERS
Design steps of synchronous counter

Design 3-bit synchronous up counter using JK flip flops.

Step 1: Find the number of flip flops.

A flip flop stores only one bit, hence for a 3 bit counter, 3
flip flops(n=3) are needed to design the counter.
Number of states = 2n = 23 = 8 states
Step 2: Choose the type of flip flop.
Since the type of flip flop is given in the problem, let us
use JK flip flops.
Step 3: Write the sequence of the counter
000, 001, 010, 011, 100, 101, 110, 111
Obtain excitation table for the counter.
• We know, the excitation table for JK flip flop
• Excitation table for the 3-bit synchronous counter is
determined from the excitation table of JK flip flop
 COUNTERS
Design steps of synchronous counter
Excitation table for JK flip flop
 COUNTERS
Design steps of synchronous counter
Step 5: Derive the flip flop input functions
 COUNTERS
Design steps of synchronous counter

Step 6: Draw the logic diagram of the counter.

 COUNTERS
3-BIT SYNC. UP COUNTER
 COUNTERS
4-BIT SYNC. UP COUNTER
 COUNTERS
4-BIT SYNC. UP COUNTER
 COUNTERS
2-BIT ASYNC. UP COUNTER
 COUNTERS
2-BIT ASYNC. UP COUNTER
 COUNTERS
3-BIT ASYNC. UP COUNTER
 COUNTERS
3-BIT ASYNC. UP COUNTER
 COUNTERS
4-BIT ASYNC. UP COUNTER
 COUNTERS
4-BIT ASYNC. UP COUNTER
 COUNTERS
4-BIT ASYNC. DOWN COUNTER
 COUNTERS
4-BIT ASYNC. DOWN COUNTER
 COUNTERS
SYNC. MOD COUNTER DESIGN
 The counter can be designed using any types of Flip flop.
But in general T-Flip flop is used to design counter.

 The use of MOD counter in to counter value for specific

number of times.

 For example, MOD-5 Counter means it can counter the

values from 0 to 4 and it get reset. So, it count in the
sequence of 000,001,0110,011,100,000,001,etc.,

 The number of flip flop required to design MOD counter is

depends on the number of count it performs.
 COUNTERS
SYNC. MOD COUNTER DESIGN

1. Determine the number of Flip-Flop needed

2. Choose the type of Flip Flop and its excitation

table

3. Determine Transition table

4. K-Map simplification procedures for driving

expressions

5. Draw the logic diagram

 COUNTERS
Example:1 Design of MOD-6 Counter using JK Flip flop
 COUNTERS
Example:1 Design of MOD-6 Counter using JK Flip flop
 COUNTERS
Example:1 Design of MOD-6 Counter using JK Flip flop
 COUNTERS
Example:1 Design of MOD-6 Counter using JK Flip flop
 COUNTERS
Example:2 Design of MOD-6 Counter using T Flip flop
 COUNTERS
Example:2 Design of MOD-6 Counter using T Flip flop
 COUNTERS
Example:2 Design of MOD-6 Counter using T Flip flop
 COUNTERS
JOHNSON COUNTERS

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 75

 COUNTERS
JOHNSON COUNTERS

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 76

 COUNTERS
JOHNSON COUNTERS

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 77

 COUNTERS
RING COUNTERS

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 78

 COUNTERS
RING COUNTERS

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 79

 COUNTERS
RING COUNTERS

MODULE-6 ECE2003 – DIGITAL LOGIC DESIGN 80

 COUNTERS
module upordown_counter( Clk, reset, UpOrDown, Count );
input Clk,reset,UpOrDown;
output [3 : 0] Count;
reg [3 : 0] Count = 0;
always @(posedge(Clk) or posedge(reset))
begin
if(reset == 1)
Count <= 0;
else
if(UpOrDown == 1) //Up mode selected
if(Count == 15)
Count <= 0;
else
Count <= Count + 1; //Incremend Counter
else //Down mode selected
if(Count == 0)
Count <= 15;
else
Count <= Count - 1; //Decrement counter
end
endmodule
 COUNTERS
Example: Mod N Counter

// # (parameter N = 10, parameter WIDTH = 4)

module modN_ctr ( input clk, input rstn, output reg[WIDTH-1:0] out);

always @ (posedge clk) begin

if (!rstn) begin
out <= 0;
end else begin
if (out == N-1)
out <= 0;
else
out <= out + 1;
end
end
endmodule
 COUNTERS
module tb;
parameter N = 10;
parameter WIDTH = 4;
reg clk;
reg rstn;
wire [WIDTH-1:0] out;

modN_ctr u0 ( .clk(clk), .rstn(rstn), .out(out));

always #10 clk = ~clk;

initial begin
{clk, rstn} <= 0;
repeat(2) @ (posedge clk);
rstn <= 1;
repeat(20) @ (posedge clk);
$finish;
end
endmodule