ASIC Design Flow

Electronic Design Process

 Design process is the process of getting IC design from

specification.

Specification IC design

9 bit  resolution  10 bit

200 MHz  conversion rate

 400 MHz

200 MHz  clock

frequency  400 MHz
Design process
Integral nonlinearity  1
LSB

. . . . . . . .
IC Design Problem

 IC Characteristics
 Area
 Speed
 Power dissipation
 Design time
 Testability
 It is impossible to design an integrated circuit at once while having
required characteristics
 The complexity is simply too high
Design Goals

 Cost
 Non-Recurring Engineering (NRE) cost
 One-time cost spent on research and design of IC after which recurring manufacturing
can be started
 Manufacturing cost
 Quality
 Design performance/area/power tradeoff
 Time-to-Market
 Design and manufacturing time
Design/Manufacturing Options

 Full-Custom Full- Semi-

Prog.
Custom Custom
 All design and manufacturing process cycles are
circuit specific Cost High Small Low
(design/manufacturing)
 Semicustom
Quality Best Low Low
 Some design and manufacturing cycles is (performance/area/power)
predefined Time-to-Market Long Short Short
 Programmable (time-to-market)

 Functionality achieved by configuring Production Volume Large Medium Small

(use cases)
(programming) already fabricated general purpose
IC

Full-Custom and Semicustom fabrication is used for Application Specific ICs

(ASIC), i.e. manufactured for specific purpose
Digital IC Design Flow
Cell description coding
(RTL)
Specification

Simulation tool Description simulation VCS

Synthesis tool Logic Synthesis Design Compiler

Formal Verification Formality
Verification tool (RTL Vs Gate level circuit)

STA tool Pre-layout STA PrimeTime

Timing
OK?

Floorplanning, IC Compiler
Physical synthesis tool
Placement & Routing

Formal Verification
Verification tool (Layout Vs.Synthesized Netlist)

STA tool Post-layout STA Star RC + PrimeTime

no Timing yes
Finished design
OK?
Specification Example
N0 Parameter description Min Typ Max Units
1. Process 3.3V IO devices in TSMC 0.11
2. Resolution 9 10 Bits
3. Conversion Rate 200 400 MHz
4. Input Clock Frequency 200 400 MHz
5. Integral Nonlinearity 1 LSB
6. Differential Nonlinearity 0.5 LSB
7. Gain Error 5 %FSR
8. Offset error 5 %FSR
9. Signal to Noise Ratio 56 62 DBc
10. Harmonic Distortion -60 DBc
11. Temperature Drift 12 ppm/C
12. Reference Voltage 1.25 V
13. Analog Input Voltage 1.6 V
14. Power Supply Voltage1 0.8 1.1 1.22 V
15. Power Supply Voltage2 3 3.3 3.6 V

16. Power Dissipation 125 180 mW

17. Operating Temperature 0 125 °C

18. Spurious Free Dynamic Range -10 dB

19. Effective Resolution Band Width 6 MHz

20. Clock jitter 28 Ps

Specification
Specification
Design Description
Circuit must turn lights when a button is pressed, or ask for recharge
if battery charge is low
N0 Parameter description Min Typ Max Units
1. Process 3.3V IO devices in TSMC 0.11 Specification is the list of
2. Voltage 1.08 1.2 1.32 V goals that should be
3. Temperature -40 125 0C
achieved in the given design.
4. Power Dissipation 100 mW
5. Die Area 2 um2

6. Clock frequency 1GHz

…. …. …. …. …. ….
…. …. …. …. …. ….
…. …. …. …. …. ….
Design Description

Design description (behavior)

Specification
must be translated to
Design Description
Architecture and Hardware
Circuit must turn lights when a button is pressed, or ask for recharge
if battery charge is low Description Language (HDL)
N0 Parameter description Min Typ Max Units understandable by EDA tools.
1. Process 3.3V IO devices in TSMC 0.11
2. Voltage 1.08 1.2 1.32 V RTL level description is used
3. Temperature -40 125 0C as input for synthesis.
4. Power Dissipation 100 mW
RTL Example
5. Die Area 2 um2

6. Clock frequency 1GHz

if button1_pressed
if (battery_charge > 10)
…. …. …. …. …. ….
turn_on_light();
…. …. …. …. …. ….
else
…. …. …. …. …. …. prompt_for_recharge();
Operating Conditions
Specification Design depends on operating
Design Description conditions
Circuit must turn lights when a button is pressed, or ask for recharge
if battery charge is low Design parameters change if
designs operates at different
N0 Parameter description Min Typ Max Units
 Process variation
1. Process 3.3V IO devices in TSMC 0.11  Voltage change
2. Voltage 1.08 1.2 1.32 V  Temperature
3. Temperature -40 125 0C

Design is designed to work at

4. Power Dissipation 100 mW different combinations of P, V, T
5. Die Area 2 um2  Fast transistors, 1.32V, -400C
 Slow transistors, 1.08V, 1250C
6. Clock frequency 1GHz
…. …. …. …. …. ….
This cases are called PVT corners
…. …. …. …. …. ….
…. …. …. …. …. ….
Process variations are usually generalized as: fast , slow, typical
Design Constraints

Specification Design goals are specified

Design Description as constraints .
Circuit must turn lights when a button is pressed, or ask for recharge
if battery charge is low Power ≤ 100 mW
N0 Parameter description Min Typ Max Units Area < 2 um2
1. Process 3.3V IO devices in TSMC 0.11 Frequency > 1 GHz
2. Voltage 1.08 1.2 1.32 V
3. Temperature -40 125 0C Design constraints are used
4. Power Dissipation 100 mW
as input for synthesis.
5. Die Area 2 um2
6. Clock frequency 1GHz
…. …. …. …. …. ….
…. …. …. …. …. ….
…. …. …. …. …. ….
Cell Based Automated Design

process begin
Process wait until not
CLOCK'stable
Design and CLOCK=1;
if(ENABLE='1') then
RTL / Logic
TOGGLE<= not
TOGGLE;
Rules end if;
end process;

Cell Library

EDA Tools

Design
Logic Simulation

 Verifying functionality and Design

timing through Simulation and description

Testbench Generation
(example: VCS-MX, VERA)
Logic Simulation

Timing
Diagrams,
Schematics,
...
Logic Simulation Steps
Design Verilog description
Compiling is the first Module test(out,in,clk);
input in,clk;
step to simulate your output out;
design. In this phase Compilation
wire a;
dff dff0(a,in,clk);
the instance hierarchy ...
is built and a binary
executable is
generated. binary executable file

Simulation phase
Simulation uses the binary
executable file to
simulate your design.

Diagrams
Basic Steps of Synthesis

Circuit description
y=(a+b)&(c⊕d)&e

Design
Logic Synthesis Compil
er a
b y
Logic Circuit
c
d
e
IC
Physical Synthesis
Compil
er

Layout of finished design

Digital IC Specification

 Description of Digital IC functionality

 With the help of Verilog or VHDL in the specification
 An example of specification line:
 if incoming_call AND line_is_available then RING;
 The specifications of contemporary Digital IC can contain millions
of lines, can be created by a collective of numerous participants
within a few months
Logic Synthesis
 Logic synthesis is the process which produces logic
circuit from circuit description
Circuit description Standard cells

y : output; AND
a,b,c : input;
y= (a+b)*c; OR

Logic synthesis

a
b
c
Logic Synthesis Data Flow

Design RTL
description

Specification Logic Synthesis Logic Circuit

Design
Constraints

Digital Standard
IP cell library
Cell Library

Building Blocks (Library)

Logic Synthesis Steps
residue = 16’h0000;
if (high_bits == 2’b10)
Design RTL description residue = state_table[index];
Technology Specific
else
Circuit is get from state_table[index] = 16’h0000;
independent one by
replacing all Translation
components by real
blocks (standard
cells). This
replacement process Technology Independent Circuit
is also called mapping

Compilation Technology
4x
and Optimization Independent Circuit is
logic circuit which fully
3x
implements function
2x 8x Technology Specific described but is built
Circuit from Generic Boolean
1x 2x
Gates.
Constraint-Driven Synthesis
Design RTL description

User can control synthesis process by

Translation
providing constraints. Constraints are took
in to account in the optimization step
Technology Independent Circuit

Compilation Design
and Optimization Constraints

Technology Specific
Circuit
Area Constraints

 Area constraints are given by limiting maximum area value

 As timing has greater priority in Design Compiler it is used to
set maximum area to zero, thus optimization achieves the
best possible area with timings met
Timing Closure and Constraints

 Problem
 In clocked environment signals on the register inputs must arrive before next reading sequence (called arrival
time)
Delay

Some
IN OUT IN OUT
Some operations New
Register data data Register
to store

CLK CLK

Clock

If Delay > Tclock second register

will not be able to store new
Clock: Both registers store new value at specific points data, which will be lost!
of time (with some frequency, like 1GHz)
Constraining Timing: Example

Delaymax= Tclk – tsetup=8ns

Clock period: Tclk = 10ns
DFF Setup time: tsetup =2ns

D Q D Q D Q
D Q DF
DFF DFF
DF F
F
CLK CLK CLK
CLK

Clock
Clock

Delayin=1ns Delaymax= Tclk – tsetup – Delayin=7ns Delayout=3ns

Delaymax= Tclk – tsetup – Delayout=5ns

Synthesis and Optimization

y=(a+b)&(c⊕d)&e
 Synthesis
 The process which converts an abstract
form of desired circuit behavior into a a
design implementation in terms of logic b y
gates c
d
 Optimization e
 Changing design to achieve design goal
(required by specification)
a
2
b 3 y
c
1
d
e
Logic Optimization

 Logic synthesis also optimizes the circuit. The problem:

 Circuit simply created from function can possibly operate not as
expected.

The delay of U1element Additional elements should be added to

will affect final result the circuit to ensure correct operation

U1
U1
U2 U2
delay
Main Optimization Trade-Offs

 Circuit design is a trade-off of Cell Power

timing, power and area

2
 Timing optimization
2.5
 Goal: small delays
3
 Power optimization
Same function: Y=a+b+c+d
 Goal: low power consumption
 Area optimization a
b a
c y b
 Goal: small area d
c
d y
e e

Total power:~6 Total power:~5

Design Constraints: Parameter Trade-off

Frequency is usually
Power replaced by delay, as the
lower the delay the larger is
frequency
Large
Optimal point Power < 100 mW
•
Area < 2 um2
• Delay < 1ns
•
• • •
Small

Short Long Delay

Design Environment of Logic Synthesis
Constraints

•clock period
RTL Code •input delay
Gate-level Netlist
(Verilog / VHDL) •output delay
(Verilog / VHDL)
•load 0.25
module CONTROL module CONTROL ….
… •………. input A, B, C;
input A, B, C; output reg X;

output reg X; …..

….. Logic Synthesis and2 U1 (.I0(B), .I1(C), .Z(T1);

if (A) (Synthesis tool) or2 U2 (.I0(B), .I1(C), .Z(T2);

mux2 U3 (.S(A),.I1(T1),.I2(T2),
X = B | C; .Z(X);
else
X = B & C;

Cell Library
(Logical Description) Physical Design
(Physical synthesis tool)
Design Compiler
Digital Standard Cell Library

 Digital standard cell library (DSCL) is a set of cells which is

used to design large ICs
 Cell number can be minimal, but the larger and more
comprehensive is the set the more flexible will be synthesis,
and the better will be the resulting circuit operation.
Digital Standard Cell Library: Gates

 Boolean logic is a set of functions defined on binary valued

variables
 Variable values may be defined in any of several ways: {1,0}, {True,False},
{On,Off}, {High,Low}, {0.8V,0V}, {VDD, VSS}
 A logic function performs transformation on a set of boolean variables
and constants
Standard Cell Specification Example

 The SAED_EDK14_CORE Digital Standard Cell Library will be built using SAED14nm 1P9M
0.8V/1.5V/1.8V design rules.
 The library will be created aimed at optimizing the main characteristics of designed integrated circuits
by its help.
 The library will include typical miscellaneous combinational and sequential logic cells for different drive
strengths.
 Besides, the library will contain all the cells which are required for different styles of low power (multi-
voltage, multi-threshold) designs. Those are: Isolation Cells, Level Shifters, Retention Flip-Flops,
Always-on Buffers and Power Gating Cells.
 The presence of all these cells will provide the support of integrated circuits design with different core
voltages to minimize dynamic and leakage power.
Low Power Design Techniques Overview

Clock Gating
Din
Register
Bank
Enable Dout
Latch

Clock

Static Multi Voltage (MV) MV with power gating

OFF

0.9V 0.9V

0.7V 0.9V 0.7V 0.9V

Design Flow Concept
Data from the
Specification previous level

Level 1
Operation
needed
Level 2
no Meets the
spec?

yes
Level n
Next level

Completed
Design
Verification

 Verification is used to check if the design object produced by

the design step is the same as the needed one

Design Design Design

Spec
Level 1 Level 2 Level n

Is it the needed Is it the same Is it the same

design? design? design?
Verification
Verification Methods

 Formal Verification
 This method mathematically proves that same design at different design levels has fully equivalent function
 Static Timing Analysis
 Path delay is calculated by summing delays of elements without simulation
 Simulation
 The behavior of object in time and space is reproduced
Formal Verification

 Formal verification checks whether two designs are

functionally equivalent or not

Formal verification
(Equivalence check)
Static Timing Analysis (STA)

 The arrival time at the input is propagated through the gates

at each level till it reaches the output

O=max[sum(B,D22),sum(C,D21)]

C D21

A D22 O

D1
B=sum(A,D1)

0 2 4 6
Gate Level Simulation

A D
 Simulation of timing behavior of logic design
B E
 Logic design description
C
 Netlist, network
 Components
 e.g. AND, OR, etc.
A
 Component interconnections
 Logic models B
 Component behavior
 Interconnect behavior C
 Signal values
 Timing models D
 Component behavior
E
 Interconnect behavior
 Signal delays
Time
Test Creation

 Automatic test patterns (ATPG) are generated for synthesized

circuit that can be used to test the design after fabrication.

Test Pattern Testing Results

applying signals measuring response

+ +
expected response checking against expectations
Physical Synthesis

 Physical synthesis is the process that produces layout of logic

circuit.
Circuit Standard cell layouts

a AND
b
c OR

Physical synthesis
Physical Synthesis Steps
Floorplanning

Global placement

Placement

Clock Tree Synthesis

Global Routing

Detailed Routing

Sign-off
Physical Synthesis
Technological Data
Logic Synthesis
(Synthesis tool) Available layers

Design Rules
Gate-level Netlist
(Verilog / VHDL)

Parasitics Models Physical Design Layout

(Physical design tool)

Design
Constraints
Physical Model
Digital Standard
IP cell library
Abstarct view
Cell Library FRAM view
Floorplanning

 During the floorplanning step the overall cell is defined, including:

cell size, supply network, etc.

Floorplan
Placement
Global Placement

Reading Get-Level
Netlists from synthesis

Global Placement

Detailed Placement

Placement optimization
Placement

 Placement – exact placement of modules (modules can be standard

cells, IPs).
 The goal is to minimize the total area and interconnect length

Cells from a Floorplan Placed

circuit design
Unit Tile

 Placement uses grid in which cells

are placed unit tile

Floorplanning ‘unit tile’ cell to build

(site)

this grid BUF FF

 Unit tile is defined by a library developer

NOR
 All the cells in the library are designed
to be multiple to unit tile INV
Physical Synthesis Circuit Optimization Example: Clock
Delay Problems
 All clock pins are driven by a single clock source
FF FF FF FF FF FF

FF FF FF FF FF FF

Clock
FF FF FF FF FF FF

FF FF FF FF FF FF
Clock Tree Synthesis (CTS)
FF FF FF FF FF FF

FF FF FF FF FF FF

FF FF FF FF FF FF
Clock

FF FF FF FF FF FF

A buffer tree is built to balance the loads and minimize the skew
Routing

 Routing connects placed cells according to schematic

 The goal is minimal impact of interconnects on circuit operation

Placed design Routed design

Global Routing

 Determining overall path of all NAND AOI

routes
 Picking channels to route DFF INV NOR

through
DFF NOR DFF
 Seeking to reduce delay,
channel widths
Detailed Routing

 Determining exactly how each NAND AOI

signal is routed through each
region DFF INV NOR

 Seeking to reduce routing

DFF NOR DFF
area
Sign-off: SI Analysis

Initial timing
Gate-level reports
netlist

Design SI analysis tool

Constraints

Saved session

Design Libraries

Net parasitics with

coupling caps in SPEF
or SBPF
Sign-off: Extraction and Verification
Timing, Power
Ideal input and Circuit
netlist(schematic Checks
netlist)

Configuration
Post-layout verification
Files
and extraction tool

Current output
Waveform
Extracted
parasitic netlist

Device models/
technology file
IC Compiler ll: Floorplanning
IC Compiler ll: Placing Macros

Applying physical
constraints

Placing macros and

standard cells

Running incremental
placement
IC Compiler ll: Placement
IC Compiler ll: CTS
IC Compiler ll: Routing
IC Compiler ll: Power Density Map

 Ideally, power
dissipation should be
distributed evenly
across the core area
 High power density in a
small area can lead to
 IR-drop
 EM
 Poor product life
IC Compiler ll: Congestion Map
Causes high local utilization
 No need to use -congestion
unnecessarily
 By default, physical synthesis tool
performs some congestion optimization
that has a reasonable chance of providing
acceptable congestion
 Congestion increases efforts of algorithm
of a congestion Gives uniform density
 On average –congestion increases runtime
by 20%
 For better correlation to post-route,
congestion-driven placement is enabled
based on GR congestion map
Thank You