Digital Timing Analysis Document

tco : Clock to Output delay of the output register.

t pd : Path propagation delay of the Data. This includes Gate and Trace delay. t pc : Path propagation delay from Clock1 to Clock2, (Clock Skew). t pc = tclock 2 tclock 1 t su : Data setup time requirement for the input register. t hold : Data hold time requirement for the input register, (normally = 0). t m arg in : Allocated timing margin. Typically one gate delay or 4ns. t pdc = t pd t pc tclk min = tco + t pdc + t su + thold + tm arg in

f max =

1 tclk min

NOTES: A systems timing margin can be improved by delaying the clock to the register2 input. This creates a positive value for tpc and provides more setup time for register2. This method does not work for a feedback circuit, such as a divide by 2. In a feedback circuit delaying the clock will improve setup for register2 but it will decrease setup for the input of the feedback register.

D1

Q1

D2

Q2

t pd
CLOCK CLOCK1 SOURCE CLOCK2

tco
CLOCK1 Q1 CLOCK2 D2 CLOCK2
(With delay)

tsu

t pd

t pc

D2