Dynamic Combinational

Circuits
• Dynamic circuits
– Charge sharing, charge redistribution
• Domino logic
• np-CMOS (zipper CMOS)

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 Dynamic Logic
• Dynamic gates use a clocked pMOS pullup
• Two modes: precharge and evaluate

2 2/3 φ 1
A Y Y Y
1 A 4/3 A 1

Static Pseudo-nMOS Dynamic

φ Precharge Evaluate Precharge

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 The Foot
• What if pulldown network is ON during
precharge?
• Use series evaluation transistor to prevent fight.
φ φ
precharge transistor
φ Y Y
Y inputs inputs
A f f
foot

footed unfooted

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 Dynamic Logic
VDD VDD

Φ Mp Φ Me
Out
In1
CL
In1 In2 PUN
In2 PDN In3
In3 Out

Me Mp CL
Φ Φ

Φn network Φp network
• Precharge
2 phase operation:
• Evaluation

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 Logical Effort
Inverter NAND2 NOR2

φ 1
Y
φ 1 φ 1
A 2
unfooted Y Y
A 1 B 2 A 1 B 1
gd = 1/3 gd = 2/3 gd = 1/3
pd = 2/3 pd = 3/3 pd = 3/3

φ 1
Y
φ 1 φ 1
A 3
Y Y
footed A 2 B 3 A 2 B 2
gd = 2/3 gd = 3/3 gd = 2/3
2 pd = 3/3 3 pd = 4/3 2 pd = 5/3

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 Dynamic Logic
• N+2 transistors for N-input function
– Better than 2N transistors for complementary static CMOS
– Comparable to N+1 for ratio-ed logic
• No static power dissipation
– Better than ratio-ed logic
• Careful design, clock signal Φ needed

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 Dynamic Logic: Principles
VDD • Precharge
Φ = 0, Out is precharged to VDD by Mp.
Φ Mp
Me is turned off, no dc current flows
Out
(regardless of input values)
CL
In1 • Evaluation
In2 PDN
In3 Φ = 1, Me is turned on, Mp is turned off.
Output is pulled down to zero depending
Me on the values on the inputs. If not,
Φ
precharged value remains on CL.

Important: Once Out is discharged, it cannot be charged again!

Gate input can make only one transition during evaluation

• Minimum clock frequency must be maintained

• Can Me be eliminated?

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 Example
VDD

Φ Mp
Out
• Ratio le s s
• No Static Po we r Cons umptio n
A • Nois e Marg ins s mall (NML)
C
• Requires Cloc k
B

Φ Me

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Dynamic 4 Input NAND Gate

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 Cascading Dynamic Gates
VDD VDD V
Φ

Mp Φ Mp
Φ In
Out1 Out2

Out1
In VTn

Out2
Φ Me Φ Me t

Internal nodes can only make 0-1 transitions during evaluation period

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 Monotonicity
• Dynamic gates require monotonically rising inputs
during evaluation φ
– 0 -> 0 A
– 0 -> 1
– 1 -> 1 violates monotonicity
during evaluation
– But not 1 -> 0 A

φ Precharge Evaluate Precharge

Output should rise but does not

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 Monotonicity Woes
• But dynamic gates produce monotonically falling
outputs during evaluation
• Illegal for one dynamic gate to drive another!
A=1

φ φ Precharge Evaluate Precharge

Y
X
A
X
X monotonically falls during evaluation
Y
Y should rise but cannot

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Reliability Problems — Charge Leakage
VDD

Φ
Φ Mp
Out
(1) CL
A t
Vout precharge evaluate
(2)

A=0
Φ Me

t
(a) Leakage sources (b) Effect on waveforms

(1) Leakage through reverse-biased diode of the diffusion area

(2) Subthreshold current from drain to source
Minimum Clock Frequenc y: > 1 MHz

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 Leakage
• Dynamic node floats high during evaluation
– Transistors are leaky (IOFF ≠ 0)
– Dynamic value will leak away over time
– Formerly miliseconds, now nanoseconds!
• Use keeper to hold dynamic node
– Must be weak enough not to fight evaluation
weak keeper
φ 1 k
X
H Y
A 2
2

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 Charge Sharing (redistribution)
• Assume: during precharge, A and B are 0, Ca is discharged
VDD • During evaluation, B remains 0 and A rises to 1
• Charge stored on CL is now redistributed over CL and Ca

Mp
Out

CL CLVDD = CL Vout(t) + CaVX

A Ma
X VX = VDD - Vt, therefore
Ca
Ca δVout(t) = Vout(t) - VDD = (VDD-Vt)
B=0 Mb CL

Cb Desirable to keep the voltage drop below threshold

Me
of pMOS transistor (why?) Ca/CL < 0.2

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 Charge Sharing
• Dynamic gates suffer from charge sharing
φ
φ
Y A
A x CY
Y
B=0 Cx Charge sharing noise

CY
Vx = VY = VDD
C x + CY

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Charge Redistribution - Solutions
VDD VDD

Mp Mbl Mp Mbl Φ
Φ Φ
Out
Out
A Ma A Ma

B Mb B Mb

Φ Me Φ Me

(a) Static bleeder (b) Precharge of internal nodes

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 Secondary Precharge
• Solution: add secondary precharge transistors
– Typically need to precharge every other node
• Big load capacitance CY helps as well
secondary
φ precharge
Y transistor
A x
B

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 Domino Logic
VDD VDD
VDD

Φ Mp Φ Mp Mr
Out1

Out2
In1 Static Inverter
In2 PDN In4 PDN with Level Restorer
In3

Φ Me Φ Me

Static inverters
between dynamic stages

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 Domino Gates
• Follow dynamic stage with inverting static gate
– Dynamic / static pair is called domino gate
– Produces monotonic outputs
φ Precharge Evaluate Precharge

domino AND
W

W X Y Z X
A
Y
B C
φ
Z

dynamic static
φ φ
NAND inverter φ φ
A W X A X
H Y =
B H Z B Z
C C

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Domino Logic - Characteristics

• Only non-inverting logic

• Very fast - Only 1->0 transitions at input of inverter

• Precharging makes pull-up very fast

• Adding level restorer reduces leakage and
charge redistribution problems

• Optimize inverter for fan-out

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 Domino Optimizations
• Each domino gate triggers next one, like a string of
dominos toppling over
• Gates evaluate sequentially but precharge in parallel
• Thus evaluation is more critical than precharge
• HI-skewed static stages can perform logic
φ

S0 S1 S2 S3
D0 D1 D2 D3
Y
H
φ

S4 S5 S6 S7
D4 D5 D6 D7

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 Dual-Rail Domino
• Domino only performs noninverting functions:
– AND, OR but not NAND, NOR, or XOR
• Dual-rail domino solves this problem
– Takes true and complementary inputs
– Produces true and complementary outputs

sig_h sig_l Meaning

Y_l Y_h
0 0 Precharged φ
inputs
0 1 ‘0’ f f

1 0 ‘1’ φ

1 1 invalid

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 Example: AND/NAND
• Given A_h, A_l, B_h, B_l
• Compute Y_h = A * B, Y_l = ~(A * B)
• Pulldown networks are conduction complements

Y_l φ Y_h
= A*B A_h = A*B
A_l B_l B_h

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 Example: XOR/XNOR
• Sometimes possible to share transistors

Y_l φ Y_h
= A xnor B A_h A_l A_l A_h = A xor B
B_l B_h

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 Domino Summary
• Domino logic is attractive for high-speed circuits
– 1.5 – 2x faster than static CMOS
– But many challenges:
• Monotonicity
• Leakage
• Charge sharing
• Noise
• Widely used in high-performance microprocessors

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np-CMOS (Zipper CMOS)
VDD VDD

Φ Mp Me
Out1 Φ

In1 PUN
In2 PDN In4
In3 Out2

Φ Me Mp
Φ

• Only 1-0 transitions allowed at inputs of PUN

• Used a lot in the Alpha design

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 np CMOS Adder
VD D VD D
VDD VDD
φ φ S1
φ φ
Ci1
A1 B1 B1 A1
B1 Ci1 A1
A1
B1
Ci2 φ
φ φ
φ
VDD
VDD
VDD φ
φ
φ B0
A0 Ci1
A0 B0 Ci0 A0
A0 B0 B0 Ci0
S0
φ φ φ
Ci0
Carry Path

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CMOS Circuit Styles - Summary

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