Optimization of behavior modeling for codesign of

embedded system
The project deals with the second module of Hardware-Software partitioning for
codesign of embedded systems. That is the optimization techniques in the
behavioral modeling for codesign of embedded systems. The partitioned software
binary in the first module will be decompiled here to hardware description
language. A partition tool is needed to be designed in binary level approach. Several
optimization techniques like dead code elimination, loop unrolling, register
allocation ect are carried out here in order to achieve large speedup generally about
2x to 10x. The advent of single-chip DSP/FPGA platforms makes such partitioning
even more beneficial. Although source code partitioning is preferable from a purely
technical viewpoint, binary-level partitioning provides several practical benefits for
commercial use. Since we are comparing the un-optimized and optimized
decompilation it is easy to show the speedup. Partitioning at the binary level makes
the method suitable for dynamic on-the-fly partitioning of software into hardware.
The basic blocks of software binaries are transformed into dataflow descriptions for
implementation of the partitioned software in hardware. As a first step, the portion
of the software binary to be transformed into hardware is identified using
instruction level profiling. The partitioned software (to be transformed into
hardware) is represented in terms of initial and final state which is described by set
of register value pairs. A CDFG representing the initial state to final state
transformation is derived by equating the final state attained in terms of algebraic
place holders which is then synthesized in hardware.