LIST OF EXPERIMENTS

SI.no. Experiment name Page

no.
1 Design of Inverting, Non-Inverting and Differential amplifiers 1

2 Integrator and Differentiator

3 Design of an Instrumentation amplifier

4 Design and Construction of Astable, Mono stable Multivibrators

using Op-Amp

5 Characteristics of PLL and its use as Frequency Multiplier

6 Design and Construction of Astable , Mono stable Multivibrators

using NE555 timer

DESIGN OF INVERTING, NON-INVERTING AND DIFFERENTIAL

AMPLIFIERS
AIM:
To design and construct a non inverting, inverting amplifier, comparator and adder circuit
using op-amp and obtain their output.
APPARATUS REQUIRED:

S.No Apparatus Range Quantity

1. Resistor 10kΩ 5
2. Op-amp IC741 1
3. Dual RPS (0-30)v 1
4. AFO - 2
5. CRO - 1
6. Bread board - 1
7. Connecting wires -

DESIGN:

LINEAR INTEGRATED CIRCUITS LAB MANUAL Page 1

 Inverting amplifier:
A = -Rf/R1
Take A = 1
Rf = R1
Choose Rf = 10kΩ, R1=10kΩ

Non inverting amplifier:

A = 1+ Rf/R1
Take A = 2
Rf = R1
Choose Rf = 10kΩ, R1=10kΩ

Adder:
Inverting Adder:
Vo= -(Rf/R1)V1-(Rf/R2)V2-(Rf/R3)V3
Take A = 1
Rf = R1
Choose Rf = 10kΩ, R1=10kΩ

Non-Inverting Adder:
Vo= (1+ Rf/R1)V1 +(1+ Rf/R2)V2+(1+ Rf/R3)V3
Take A = 2
Rf = R1
Choose Rf = 10kΩ, R1=10kΩ

Comparator:
Vo= +Vsat if V2>V1
Vo= -Vsat if V1>V2

PROCEDURE:

Inverting and Non-inverting amplifier:

1. Connections are made as per the circuit diagram.
2. Apply the input voltage using AFO or RPS.
3. The output is noted and plot the graph.
4. Then calculate the gain value.

Adder:
1. Connections are made as per the circuit diagram.
2. Apply the input voltage v1, v2, v3using RPS, the output is noted.
3. This is repeated for different values of v1, v2, v3.
4. The results are tabulated.

Comparator:
1. Connections are made as per the circuit diagram.

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 2. Apply the two periodic signal using AFO.
3. Note the output square wave form and plot the graph.

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 CIRCUIT DIAGRAM

INVERTING AMPLIFIER NON INVERTING AMPLIFIER

R2 R4
1k 1k
R1 R3
4

4
2 1 2 1
- OS1 - OS1
V-

V-
1k U1 6 1k U2 6
OUT OUT
3 5 3 5
+ OS2 + OS2
7

7
uA741 CRO AFO uA741 CRO
V+

V+
AFO

0 0

ADDER COMPARATOR

R 1
1k
V1 R 3
1k U 1 R 5 U 2
7

Vin 3 5
4

+ O S2
V+

V2 R 2 2
- O S1
1
1k V0
V-

6
1k
6 V0 R 6 uA741O U T
V3 uA741O U T 2 1
- O S1
1k
R 4 3
+ O S2
5 Vref 1k
4
V-
7
V+

RESULT:

Thus the non-inverting, inverting, adder and comparator circuits are designed and constructed
using op-amp and their outputs are obtained.

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 2. INTEGRATOR AND DIFFERENTIATOR

AIM:
To construct and test the integrator and differentiator circuit. Draw the waveforms

APPARATUS REQUIRED:

S.No Apparatus Range Quantity

1. Resistor 10kΩ,1kΩ 2,2

2. Capacitor 470pF, . 1
1nF,1μF 1,1
3. Op-amp IC741 1
4. Dual RPS (0-30)v 1
5. AFO - 2
6. CRO - 1
7. Bread board - 1
8. Connecting wires - -

DESIGN:
Integrator:
Vo= -(1/R1*Cf) *∫Vin dt
Differentiator:
Vo= -R1Cf * dv/dt

PROCEDURE:
Integrator:
1. Connections are made as per the circuit diagram.
2. Apply the square or sine input signal at high frequency using AFO.
3. Note the corresponding output waveforms and plot the graph.

Differentiator:
1. Connections are made as per the circuit diagram.
2. Apply the square or sine input signal at low frequency using AFO.
3. Note the corresponding output waveforms and plot the graph.

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CIRCUIT DIAGRAM

INTEGRATOR DIFFERENTIATOR

R3

1k
C2 C3

1n 1n

R1 C 1 uA741 R2 C 4 uA741
4

4
2 1 2 1
- OS1 - OS1
V-

V-
1k 1n 1k 1n
6 6
OUT OUT
3 5 3 5
+ OS2 + OS2
7

7
U3 U4
CRO AFO CRO
V+

V+
AFO

RESULT:
Thus the integrator and differentiator circuits are constructed and tested. The wave forms
are drawn.

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 3. MULTIVIBRATOR USING 555 TIMER
AIM:
To design and construct the astable and mono stable multivibrator using 555 timer. Draw
the waveform.
APPARATUS REQUIRED:

S.No Apparatus Range Quantity

1. Resistor 6.8kΩ,10kΩ 1,2

470Ω 1
2. Capacitor 470pF, . 1,1
1nF,1μF
1
NE555
3. Timer IC 1
-
4. RPS 1
-
5. AFO 1
(0-30)v
6. CRO 1
-
7. Bread board 1
-
8. Connecting wires -

DESIGN:
Astable multivibrator:
For 50% duty cycle:
Tc= 0.69(Ra+Rb)*C
Td= 0.69Rb* C
T = Tc+Td
T = 0.69(Ra+2Rb)*C
f = 1/T = 1.45/(Ra+2Rb)*C
% Duty cycle D = Td/T*100
D = Ra/(Ra+2Rb)*C

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 Let Tc = Td = 0.05 msec
Choose C = 10nf
0.05*10-3 = 0.69(Ra+Rb)*10n
Therefore Ra+Rb = 7.215k
Choose Ra=470Ω
Rb=6.8kΩ

Monostable Multivibrator:
Tp = 1.1 RC
For Tp = 0.1ms
Choose C= 0.01μF
To Find R
R =Tp/1.1C=10KΩ

PROCEDURE:
Astable multivibrator:
1. Connections are made as per the circuit diagram.
2. The output waveforms are viewed through CRO.
3. The voltage across the capacitor and that at the output terminal is measured
and the waveforms are drawn.
Monostable multivibrator:
1. Connections are made as per the circuit diagram.
2. A low frequency trigger pulse is applied.
3. The output waveforms are viewed through CRO.
4. The voltage across the capacitor and that at the output terminal is measured
and the waveforms are drawn.

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ASTABLE MULTIVIBRATOR:

v cc

R 1
1k 8 4
7
R 2 3 o/p
1k
555
6

2
1 5
C 1
1n C 2
1n

MONOSTABLE MULTIVIBRATOR:

vcc

R2
1k 8 4
7
3 o/p
6 555
C3 D1

I/P
2
1n DIODE 1 5
C1
R3 1n C2
1k 1n

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RESULT:
Thus the astable and mono stable multivibrator using 555 timer are designed and the
waveforms are drawn.

5. CHARACTERISTICS OF PLL
AIM:
To design a PLL circuit and determine the lock in range and capture range.
APPARATUS REQUIRED:

S.No Apparatus Range Quantity

1. Resistor 6.8kΩ 1
2. Capacitor 1nF,1μF 2,1
3. PLL IC IC565 1
4. Dual RPS ±15v 1
5. AFO - 1
6. Bread board - 1
7. Connecting wires

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PROCEDURE:
1. Connections are made as per the circuit diagram.
2. Measure the free running frequency of VCO at pin 4, with the input signal vin
set equal to zero. Compare it with the calculated value = 0.25/RtCt.
3. Now apply the input signal of 1V square wave at a 1khz to pin 2. Connect one
channel of the scope to pin 2 and display this signal on the scope.
4. Gradually increase the input frequency till the PLL is locked to the input
frequency. This frequency f1 gives the lower end of the capture range. Go on
increasing the input frequency, till PLL tracks the input signal, say, to a
frequency f2. This frequency f2 gives the upper end of the lock range. If input
frequency is increased further, the loop will get unlocked.
5. Now gradually decrease the input frequency till the PLL is again locked. This is
the frequency f3, the upper end of the capture range. Keep on decreasing the
input frequency until the loop is unlocked. This frequency f4 gives the lower
end of the lock in range.
6. The lock range fL = (f2-f4). Compare it with the calculated value of 7.8f0/12.
Also the capture range is fC = (f3-f1).Compare it with the calculated values of
Capture range.
∆Fc=± [fl/ (2) (3.6) (103)*C] 1/2
PHASE LOCKED LOOP:

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 +VCC

R1
6.8k C2
C1 1nF

0.001uF

10 8

INPUT 2 7

IC 565 OUTPUT
3 4

1 9 5

C3
0.01uF

-VCC

RESULT:
Thus the characteristics of PLL are studied and the capture range& lock in range are
determined.

6. FREQUENCY MULTIPIER USING PLL

AIM:
To construct a frequency multiplier circuit using PLL.
APPARATUS REQUIRED:

S.No Apparatus Range Quantity

1. Resistor 2,10,4.7 kΩ 1

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 2. Potentiometer 20k 1
3. Capacitor 1,10nF,1pF 1,1,1
4. 4-BitBinaryCounter IC7490 1
5. PLL IC IC565 1
6. Transistor 2N2222 1
7. Dual RPS ±15v 1
8. AFO -
9. Bread board -
10. Connecting wires

PROCEDURE:
1. Connections are made as per the circuit diagram.
2. Set the input signal at 1volt square wave at 500 Hz.
3. Vary the VCO frequency by adjusting the 20kΩ potentiometer till the PLL is
locked. Measure the output frequency. It should be 5 times the input frequency.
4. Repeat the steps 2, 3 for different input frequency.

FREQUENCY MULTIPLIER USING PLL:

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 +VCC

R 1
20k C 2
C 1 1nF

0 .0 0 1 u F

10 8
INPUT 2 7
OUTPUT
4
IC 565 +VCC
3 5 R 2
1k R 3
11
1 9 5 1 1k
2 3 6 7 10
1 Q 1
2N 2222A

C 3
0 .0 1 u F

-VCC

RESULT:
Thus the frequency multiplier is constructed using PLL and checked for various
frequencies

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