A 10-bit Low-Power 10MS/s Differential Successive Approximation

Analog to Digital Converter

Ivan T. Bogue, Ruba T. Borno, and Joseph A. Potkay

Department of Electrical Engineering and Computer Science, Analog to Digital Conversion Ciruits,
University of Michigan, Ann Arbor, Michigan 48109-2122

Abstract – This paper presents the design, analysis, and on top of the capacitor array and prevents the offset from
simulation results of a 10-bit, 4mW, 10Ms/s completely affecting the comparator output. During the conversion
differential successive approximation analog-to-digital
phase, shown in Fig. 1(b), the comparator is clocked and
converter (SAR ADC) utlizing a .35µm CMOS processing
technology. The ADC achieves a maximum DNL of less than the comparator output values are loaded into the logic
0.4LSB, an INL less than 0.5LSB, an SNDR of 45dB and a block which controls the switches in the capacitor array.
THD of 46dB at an input frequency of 1.25MHz. The ADC
also incorporates an integrated current reference that was
designed to offset circuit variations with supply and
temperature.

I. INTRODUCTION
Successive approximation register ADCs are preferred
to pipelined or subranging ADCs due to their decreased
power dissipation and smaller area. High speed implemen-
tations of SAR ADCs have been instantiated in a wide
range of demanding applications such as video[1][2]. Such
implementations require a minimum sample rate of 10Ms/
s. This paper describes a high speed differential SAR ADC
that utilizes charge redistribution on an array of capacitors
for a neglegible offset voltage[3]. Optimization techniques
such as a low power gain stage and a temperature and sup-
ply voltage stabilizing current reference are included for
maximum performance.
(a) (b)
Fig. 1. Differential SAR ADC topology: (a) Sample phase (b)
II. DIFFERENTIAL SAR CIRCUIT DESCRIPTION Conversion phase
A. Topology and Operation The capacitor array is clocked at 110MHz. For a 10-bit
resolution, the ADC requires 10 clock cycles with a sample
A differential SAR topology was implemented due to rate of 10Ms/s. As shown in Fig. 2, the whole conversion
desired characteristics of common mode noise rejection takes 11 clock cycles. The first clock cycle is when the
and stability with varying power supply. The main compo- sample is taken with the buffer connected in a unity gain
nents of the designed differential SAR include two capaci- configuration. The following 10 clock cycles are when
tor arrays, a single buffer, a single comparator, and some charge redistribution takes place and 10-bits are output
digital logic to control capacitor switches. Fig. 1 shows an from the ADC. Comparator decisions are made just before
overview schematic of the differential SAR ADC topology. the falling edge of the clock after the capacitor charges
The SAR ADC has two phases of operation: sample and have been given nearly a full clock cycle to settle.
conversion.
In the sample phase, shown in Fig. 1(a), the analog volt-
ages, Vin+ and Vin- are connected to the capacitor arrays
and the input voltages are stored. The buffer is set in unity
gain feedback as switches S1 are closed. This unity gain
configuration of the buffer places the input referred offset

Fig. 2. Timing Diagram of 10Ms/s 10-bit SAR ADC
B. Dual Capacitor Array
The dual capacitor array topology is presented in Fig. 3.
This topology was used to minimize the value of the MSB
capacitor and maximize the value of the LSB capacitor,
while reducing the total capacitance value from an array
that does not contain a coupling capacitor, Cc[6]. Capacitor
switches were controlled by outputs from the control logic.
Fig. 3. Dual capacitor array topology
C. Comparator Description
The comparator consists of two parts: a pre-amp buffer
and a latching comparator. The comparator is a lower
power, faster version of the differential comparator first
described by Yin in [5]. The comparator requires two non-
overlapping clocks and can easily operate over 200MHz
and at power levels below 300µW. The designed compara-
tor has an input offset voltage standard deviation, σCOMP,
of 10mV. However, the structure is not suitable for unity
gain feedback during input referred offset cancellation.
However using a gain stage or pre-amp before the compar-
ator allows offset cancellation to be performed.
The pre-amp, shown in Fig. 4, has a number of advan-
tages in addition to performaing offset cancellation. First,
it provides additional gain, thereby relaxing the constraints
of the latching comparator. Next, it reduces the effective
offset voltage of the latching comparator, when referred to
the capacitor array. It should be noted that this offset volt-
age is reduced by a factor A, where A is the gain of the pre-
amp. Next, it serves to isolate the capacitor array from
comparator, which reduces clock feed through from the
comparator. Finally, the offset of the pre-amp can be com-
pensated by applying unity gain feedback during the sam-
pling period. This causes the offset voltage of the
comparator to appear across the capacitor array. Over-
all,the pre-amp should have some gain inorder to reduce
the noise and offset of the latching comparator. Addition-
ally, the per-amp should also have a high 3dB frequency
for fast open loop settling time to stablize the comparator
inputs to 10-bit accuracy. However, these important speci-
fications can vary with temperature and variations in the
supply voltage. The current reference was designed to
counteract these variations.
Fig. 4. Pre-Amp (buffer) schematic
D.Current Reference
A self-biased low-current reference generator was
instantiated in the comparator and the buffer. Fig. 5 shows
a schematic of the current reference. Desired current val-
ues of approximately 20µA were achieved following the
relationship presented in (1):
1 2 1 1 - (1)
I REF = --- ---- ⋅ -------------  1 – -------
R k′  W  m
-----
 L1
where m > 1 and is calculated using (2).
 L-
 ----
 W 1
m = ------------- (2)
L-
 ----
 W 2

The ideal current mirror of pmos transistors M3 and M4

equalizes the current in both legs of the circuit and Vb is
drawn from the diode connected gate of M4. The value of
the resistor is selected such that its positive temperature
coefficient will enhance the overall positive temperature
coefficient of the circuit.

M3 M4
Fig. 6. Gain (dB) vs. Frequency (Hz) plotted for Temperature
values 100oC, 27oC, and 0oC. A change of less than 2.7% across
the range of temperatures was realized.

M2 M1

Fig. 5. Current reference schematic. Vb is bias voltage con-

nected for the pre-amp and comparator circuits.

Note that the minimum gain(dB) was achieved at the tem-

perature of 27οC, which shows that optimal performance
was intentionally realized at the nominal operating temper-
ature. The current reference circuit was optimized to pro-
vide an 8% increase in current over a temperature sweep of
0 o C to 100 ο C. This positive temperature coefficient
counters the negative temeprature coefficient of the buffer.
The temperature stability of the buffer using the current Fig. 7. Gain (dB) vs. Frequency (Hz) plotted for supply volt-
age values 2.97V, 3.3V, and 3.63V.
reference is shown in Fig. 6. Fig. 7 shows the stability of
the buffer using the current reference with a +/-10% of
3.3V supply voltage.
III. CIRCUIT ANALYSIS

A. Capacitor Array Model

The equivalent circuit of the capacitor array is shown in

Fig. 8. The five switches connected to the MSB capacitor
and the next four capacitors can be modelled as an ideal
voltage source capable of producing a 5-bit DAC output
voltage (MSB DAC) over the range Vref- to Vref+. Simi-
larly, the switches connected to the other five capacitors is
also represented as an ideal 5-bit DAC (LSB DAC). The
coupling capacitance C c, divides the output of the LSB
DAC by 64 producing the overall 10-bit output of the
capacitor array. Cc can have an error of +/-0.2% without
significantly affecting the ADC performance[6]..
Fig. 8. Equivalent circuit of capacitor array
B. Capacitor Mismatch Analysis
It is desirable to have a small total capacitance in the
array due to speed and area considerations, however,
capacitor mismatch typically increases as capacitor size
decreases. For this reason, MATLAB was used to deter-
mine the effect of capacitor mismatch on the maximum
DNL of the SAR ADC.
For this simulation, a differential (dual capacitor array)
topology was used and each capacitance was assumed to
consist of a parallel combination of unit size capacitors.
The standard deviation of the unit capacitor, σCAP, was
then varied and the maximum DNL was calculted by aver-
aging the maxium DNL for ten different runs. The results
of the simulations are shown in Fig. 9, and the graph exhib-
its a sharp degredation in performance for σCAP greater
than 0.1. .
Fig. 9. DNL vs. σCAP.
The reason that such large values of σCAP are tolerable is
that the variation in unit capacitors tends to get averaged
out for capactitors composed of the combination of several
unit sized capacitors. σCAP was assumed to be close to
0.1% and the maximum DNL can be expected to be less
than 0.1 LSB due to capacitor mismatch
C. Capacitor Array Time Constant
The switches and capcacitors used in the capacitor array
have to be sized so that the charge applied to the capacitors
settles in the required time. During sampling, Vin is aplpied
to the cap array. In the conversion phase, the voltage on the
top plate of the capacitors also sees a time constant.
Assuming that the voltage source has negligible series
resistance these two time constants are roughly equal and
can be given as
(3)
τ P = R 0N C T
where RON is the resistance of the switch and CT is the total
capacitance of the array.
D.Pre-Amp Stage Settling Requirements
The settling time of the buffer is critical for system accu-
racy, where its gain is important for offset and noise reduc-
tion. For a complete analysis of settling, the operation in
both the sampling phase and the successive approximation
phase should be considered.
Fig. 10. Differential voltage input to pre-amp and comparator.
In the sampling phase, the pre-amp is connected in unity
gain and as a result, its output is connected to the capacitor
array. Normally, this would severly degrade the settling
time of the comparator as given in (4)[5]. However, as can
be seen in Fig. 10, the voltage at the input of the pre-amp
after a conversion is the same as the voltage when the pre-
amp is in unity gain feedback, and minimal settling is nec-
essary during the sampling phase. This is a significant
advantage of the chosen topology, since the bandwidth
requirements of the pre-amp can be relaxed considerably,
saving power.
During the successive approximation phase, the pre-amp
is in an open loop configuration and its time constant is
determined by its main pole. However, in order to nor-
mally determine the settling requirements of the pre-amp,
the capacitor array must also be considered, because the
capacitor array and the pre-amp form a cascaded system
where each have their own time constant. This cascaded
system then has an overall time constant that must be small
enough to allow settling to within 10-bit accuracy in the
required time. However, in this case, the time constant of
the capacitor array is much less than the time constant of
the pre-amp and can be neglected in the overall system.
For the pre-amp, the time constant is given as:
IV. RESULTS
A. Results
The 10-bit converter was designed in a 0.35µm CMOS
technology. The overall area of the circuit is 0.3mm2. The
resistor used in the current reference is implemented using
a poly resistor. The power dissipation of the is 4mW from a
3.3V supply. A comparable single ended converter was
also designed. This had a power consumption of 2.5mW.
During evaluation the ADC was connected with the
Vin+ configured as a slowly increasing ramp and Vin-
slowly decreasing. The output from the ADC was imported
into MATLAB where the linearity was calculated.

2C L (4)
τ P = R 0 C L = ---------------------------------------
-
( λ N + λ P ) ⋅ I REF

where R0 is the output resistance of the pre-amp, CL is out-

put capacitance of the pre-amp, including loading from the
comparator, IREF/2 is the DC current in each side of the
differential pair, and λN and λP are channel length modula-
tion coefficients for the NMOS load transistor and PMOS
input transistor, respectively.
The settling of the output will be determined by the
exponential decay that is due to the time constant given
above. To achieve N-bit accuracy, the exponential decay
must be within 1/2N of its final value:
Fig. 11. INL plot of SAR ADC taken at 10codes/sample.
t-
 – ---- 1 (5)
 τ P < -----N-
e 2

where settling time of the output. Combining (4) and (5)

and simplifying gives:

t (6)
R 0 C L < -----------------
N ⋅ ln 2

Assuming that the load capacitance is dominated by the

loading due to the comparator, 10-bit resolution, and a con-
servative settling time of 7.5ns (for a 9.09ns period), this
results in a required output resistance for the pre-amp, R0,
of less than 26kΩ, which corresponds to a 3dB frequency
of 147MHz. For the designed pre-amp, the current refer-
ence and device sizes were designed in parrallel provide a
3dB frequency over 150MHz over all operating tempera-
tures and supply voltages, and a low frequency gain of
approximately 20dB.
Fig. 12. DNL plot of SAR ADC taken at 10codes/sample.
The INL of the converter for the first seventeen codes is Technology .35µm CMOS
shown in Fig. 11. The maximum INL was measured as SNDR (1.25MHz) 45dB
0.4LSB. Fig. 12 shows the DNL plot where a maximum Supply Voltage 3.3V +/-10%
value of 0.4LSB was measured. Power Consumption 4mW
At 10Msample/s with a 1.25MHz full scale sinusoidal Area 0.3mm2
input, the measured signal-to-noise-and-distortion ratio Table I: Summary of Results
(SNDR) is 45dB or 7.2 effective bits. The measured total
harmonic distortion (THD) is 46dB. Fig. 13 shows the cor- V. SUMMARY OF RESULTS
responding fast Fourier transform (FFT).
The simulation results are summarized in Table I.

VI. CONCLUSION
This paper presented the design, analysis and simulations
for a 10-bit SAR capable of operating at a sampling fre-
quency larger than most state of the art commercial SAR
ADC’s. Such an ADC may find applications in both high
end video applications and in high speed sensor systems. It
performed with a maximum INL less than 0.5LSB over the
range of tested codes and with a ENOB of 7.2 bits at an
input frequency of 1.25MHz.

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